Verification Engineer, SoC/ASIC | UVM & SystemVerilog

Efficient Computer; San Francisco, Pittsburgh, Austin (CA, Allegheny County, TX); On-site; USD 130,000 - 180,000; Full time

Benefits offered by this job

10% annual bonus

Equity

401(k) match

Company-paid benefits

Paid parental leave

Flexibility

Job summary

Efficient Computer is hiring a Design Verification Engineer to own the functional verification of blocks and subsystems in our SoC. You will work with senior DV engineers, RTL designers, and architects to build testbenches, close coverage, and find bugs before silicon ships.

This role offers growth as we move from initial product development to market release and scaled volume production, with a strong emphasis on automation, coverage, and sign-off readiness.

Qualifications

• Experience in ASIC/SoC DV with tapeout projects.
• Hands-on with UVM testbenches and SystemVerilog.
• Experience defining functional coverage and driving closure.
• Knowledge of Python for test automation.
• Strong debugging using waveforms and logs.

Responsibilities

• Develop and maintain UVM testbenches, sequences, and tests for block- and subsystem-level verification.
• Write verification plans from design specifications in collaboration with design and architecture teams.
• Write SystemVerilog assertions and functional coverage models, driving coverage to closure.
• Debug simulation failures with designers to root-cause and fix issues.
• Contribute to regression infrastructure, automation, and dashboards that track verification progress.
• Support gate-level simulation and other sign-off activities.

Skills

UVM/SystemVerilog

Python scripting

Communication

Education

Bachelor’s or Master’s/PhD in Electrical/Computer Engineering

Tools

JasperGold or similar

Job description

Efficient Computer is hiring a Design Verification Engineer to own the functional verification of blocks and subsystems in our SoC. You will work with senior DV engineers, RTL designers, and architects to build testbenches, close coverage, and find bugs before silicon ships.

This role offers growth as we move from initial product development to market release and scaled volume production, with a strong emphasis on automation, coverage, and sign-off readiness.