ASIC Verification Engineer

Amentum; Crane (IN); Presencial; USD 85 000 - 100 000; Tempo integral

Vantagens oferecidas por esta oferta de emprego

Health insurance

401(k) matching

Paid time off

Educational reimbursement

Parental leave

Resumo da oferta

Amentum seeks a Computer Engineer to verify ASICs and/or FPGAs for high‑reliability, security‑focused systems for DoD customers. You will develop verification plans, build reusable SystemVerilog/UVM components, and automate EDA flows.

The role includes regression testing, debugging, and collaboration with RTL and integration teams to ensure robust designs. Minimum requirements include a degree in Computer or Electrical Engineering and experience with SystemVerilog and RTL concepts; DoD clearance

Qualificações

• Bachelor’s or graduate degree in Computer/Electrical Engineering.
• SystemVerilog and RTL concepts required/familiar.
• SVA or assertion-based verification beneficial.

Responsabilidades

• Verify ASICs/FPGA for high-reliability and security-focused apps.
• Develop verification plans based on design requirements.
• Build and maintain SystemVerilog/UVM testbenches and components.
• Create directed and constrained-random tests.
• Develop assertions, drivers, monitors, scoreboards, and coverage models.
• Run simulations/regression and debug failures.
• Review waveforms/logs/coverage to identify root causes.
• Collaborate with RTL/design teams; automate EDA flows and regressions.

Conhecimentos

SystemVerilog

VHDL familiarity

RTL concepts

SVA (SystemVerilog Assertions)

Python/Scripting

Formação académica

Bachelor’s or graduate degree in Computer or Electrical Engineering

Ferramentas

EDA tools (Siemens Cadence Synopsys)

SystemVerilog/UVM testbenches

Descrição da oferta de emprego

Amentum is seeking a Computer Engineer to support verification of ASICs and/or FPGAs for high-reliability and security-focused systems for our Department of War customers. The engineer will develop and execute verification plans, build and maintain test environments, analyze results, and help ensure designs are free of functional flaws and security-relevant weaknesses. This role also supports automation of EDA tool flows and regression activities.

Duties and Responsibilities:

• Perform verification of ASICs and/or FPGAs for high-reliability and security-focused applications
• Develop verification plans based on design requirements and architecture documentation
• Build and maintain SystemVerilog/UVM testbenches and reusable verification components
• Create directed and constrained-random tests to validate functionality and corner cases
• Develop assertions, drivers, monitors, predictors, scoreboards, checkers, and coverage models
• Execute simulations and regression test suites; analyze and debug failures
• Review waveforms, logs, and coverage data to identify root causes and drive closure
• Collaborate with RTL design, integration, and other engineering teams to resolve issues
• Support automation of EDA flows, regressions, and reporting through scripting
• Document verification results, defects, and test status for technical reviews

Minimum Requirements:

• Bachelor’s or graduate degree in Computer Engineering or Electrical Engineering 1-5 years of experience
• SystemVerilog; VHDL familiarity beneficial
• Digital design fundamentals and RTL concepts
• Directed & Constrained random verification
• SystemVerilog Assertions (SVA) or assertion-based verification
• Functional and code coverage analysis
• Debug using waveforms and simulation logs
• Scripting in Python, Tcl, Bash, or similar languages
• Familiarity with common digital interfaces and subsystem concepts (e.g., UART, SPI, I2C, MIPI, LVDS, DMA)
• Experience with EDA tools from Siemens, Cadence, Synopsys, or similar vendors
• Understanding of ASIC design and verification flow
• Ability to obtain and maintain DoD Secret Clearance (please note: US Citizenship is required to obtain a US secret clearance)

Preferred Qualifications:

• Active Secret Clearance
• Universal Verification Methodology (UVM)
• ASIC verification methodologies and testbench creation
• Experience with formal verification methods
• Familiarity with logic equivalence checking (LEC)
• Exposure to clock-domain crossing (CDC) or reset-domain crossing (RDC) analysis
• Knowledge of hardware security verification principles
• Experience with DFT or production test concepts, including ATPG vectors
• Familiarity with Automated Test Equipment (ATE) workflows
• Understanding of STIL/WGL vector syntax
• Experience debugging simulated versus measured waveform discrepancies
• Familiarity with layout versus schematic (LVS), design rule check (DRC), and broader ASIC signoff activities

Compensation Details:

$85,000-$100,000 annually

The compensation range or hourly rate listed for this position is provided as a good-faith estimate of what the company intends to offer for this role at the time this posting was issued. Actual compensation may vary based on factors such as job responsibilities, education, experience, skills, internal equity, market data, applicable collective bargaining agreements, and relevant laws.

Benefits Overview:

Our health and welfare benefits are designed to support you and your priorities. Offerings include:

• Health, dental, and vision insurance
• Paid time off and holidays
• Retirement benefits (including 401(k) matching)
• Educational reimbursement
• Parental leave
• Employee stock purchase plan
• Tax-saving options
• Disability and life insurance
• Pet insurance

Note: Benefits may vary based on employment type, location, and applicable agreements. Positions governed by a Collective Bargaining Agreement (CBA), the McNamara-O'Hara Service Contract Act (SCA), or other employment contracts may include different provisions/benefits.

Original Posting:

11/02/2026 - Until Filled

Amentum anticipates this job requisition will remain open for at least three days, with a closing date no earlier than three days after the original posting. This timeline may change based on business needs.

Amentum is proud to be an Equal Opportunity Employer. Our hiring practices provide equal opportunity for employment without regard to race, sex, sexual orientation, pregnancy (including pregnancy, childbirth, breastfeeding, or medical conditions related to pregnancy, childbirth, breastfeeding), age, ancestry, United States military or veteran status, color, religion, creed, marital or domestic partner status, medical condition, genetic information, national origin, citizenship status, low-income status, or mental or physical disability so long as the essential functions of the job can be performed with or without reasonable accommodation, or any other protected category under federal, state, or local law. Learn more about your rights under Federal laws and supplemental language at Labor Laws Posters.