Senior FPGA/ASIC Verification Engineer — SystemVerilog/UVM

MissionHires; City of Rochester (NY); Sur place; USD 100 000 - 130 000; Plein temps

Résumé du poste

MissionHires is looking for an experienced FPGA/ASIC Verification Engineer to verify and validate FPGA-based embedded communication systems. The position involves crafting verification plans, self-checking testbenches using SystemVerilog, and collaborating to meet system requirements.

The ideal candidate will have a Bachelor's degree with significant experience in FPGA/ASIC verification, knowledge of UVM methodologies, and the ability to process security clearances. This role is essential for ensuring the quality and functionality of advanced communication systems.

Qualifications

• 6+ years of relevant FPGA/ASIC verification experience.
• Experience developing embedded system solutions.
• Ability to obtain and maintain US Security Clearance.

Responsabilités

• Perform design verification and validation of FPGA systems.
• Develop detailed verification test plans.
• Create self-checking testbenches using SystemVerilog.
• Collaborate with cross-functional teams.

Connaissances

SystemVerilog

UVM/OVM methodology

FPGA/ASIC development

Debugging FPGA firmware

Scripting (Bash, Python)

Formation

Bachelor's degree or equivalent experience

Description du poste

MissionHires is looking for an experienced FPGA/ASIC Verification Engineer to verify and validate FPGA-based embedded communication systems. The position involves crafting verification plans, self-checking testbenches using SystemVerilog, and collaborating to meet system requirements.

The ideal candidate will have a Bachelor's degree with significant experience in FPGA/ASIC verification, knowledge of UVM methodologies, and the ability to process security clearances. This role is essential for ensuring the quality and functionality of advanced communication systems.