ASIC/RTL Modeling Engineer — SV/UVM (San Jose Onsite)

Experis (Austria); San Jose (CA); On-site; USD 93,000 - 133,000; Full time

Benefits offered by this job

Fully onsite in San Jose, CA

Collaborative cross‑functional team

Job summary

Semiconductor Industry is seeking an ASIC/RTL Design Engineer to join the team onsite in San Jose, CA. The role focuses on creating SystemVerilog behavioral models for analog/mixed-signal circuits within a UVM verification flow, translating schematics to model requirements, and balancing fidelity with speed.

You will debug issues using waveforms and ensure model interfaces align with RTL and testbenches, collaborating with analog, RTL, and verification teams on high‑speed SerDes and SoC IP

Qualifications

• Hands-on experience writing behavioral models of analog circuits in SystemVerilog.
• Working knowledge of analog and mixed-signal fundamentals and SystemVerilog UVM.
• Proven ability to debug simulation failures using waveforms and trace analysis.
• Ability to read schematics and netlists to define model behavior.
• Familiarity with high-speed interface standards; LTspice/HSPICE desirable.

Responsibilities

• Build behavioral models of analog circuits in SystemVerilog for UVM environments.
• Translate schematics and circuit specs into model requirements for SerDes and IP verification.
• Define model architecture and balance fidelity with simulation speed.
• Write and validate behavioral models of analog blocks against transistor-level results.
• Debug simulation failures across model, RTL, and testbench; document interfaces.

Skills

Analog SV modeling

SystemVerilog UVM

Waveform debugging

Schematics/netlists reading

High-speed interfaces

LTSpice/HSPICE familiarity

Tools

LTspice

HSPICE

VCS

Job description

Semiconductor Industry is seeking an ASIC/RTL Design Engineer to join the team onsite in San Jose, CA. The role focuses on creating SystemVerilog behavioral models for analog/mixed-signal circuits within a UVM verification flow, translating schematics to model requirements, and balancing fidelity with speed.

You will debug issues using waveforms and ensure model interfaces align with RTL and testbenches, collaborating with analog, RTL, and verification teams on high‑speed SerDes and SoC IP