ASIC/RTL Design Engineer

Delta System & Software, Inc.; San Jose (CA); Presencial; USD 120.000 - 180.000; Jornada completa

Descripción de la vacante

Delta System & Software, Inc. seeks a Modeling Engineer to develop behavioral models of analog and mixed-signal circuits in SystemVerilog for a high-speed SerDes and SoC IP verification environment.

You will collaborate with analog designers, RTL teams and verification engineers to define model fidelity, architecture and interfaces, and to debug and document model behavior across CMOS processes. Hands-on experience with SystemVerilog/UVM and high-speed interface standards is required.

Formación

• Hands-on experience writing behavioral models of analog circuits in SystemVerilog.
• Working knowledge of analog and mixed-signal circuit fundamentals and of the SystemVerilog UVM methodology, with proven skill debugging failures in simulation and waveforms.
• Familiarity with high-speed interface standards is a plus.

Responsabilidades

• Reading schematics, netlists and circuit specifications to define what each model must capture
• Developing model architecture and accuracy targets, balancing fidelity against simulation speed
• Writing behavioral SystemVerilog models of analog blocks
• Debugging simulation failures and finding the root cause in the model, RTL or testbench
• Documenting model behavior, limitations and interfaces
• You will build behavioral models of analog and mixed-signal circuits (PLLs, clocking, ADC/DAC, TX/RX analog front ends, calibration loops) in System Verilog.
• Those models drop into a System Verilog UVM verification environment used for high-speed SerDes and SoC IP.
• You will work closely with analog circuit designers, RTL designers and verification engineers.
• Successful candidates will be responsible for leading, and participating in, the modeling and verification of leading-edge designs in advanced CMOS processes.

Conocimientos

Analog modeling

SystemVerilog

Verification engineering

Debugging simulations

Educación

Herramientas

SystemVerilog

UVM

Descripción del empleo

• You will build behavioral models of analog and mixed-signal circuits (PLLs, clocking, ADC/DAC, TX/RX analog front ends, calibration loops) in System Verilog.
• Those models drop into a System Verilog UVM verification environment used for high-speed SerDes and SoC IP.
• You will work closely with analog circuit designers, RTL designers and verification engineers.
• Successful candidates will be responsible for leading, and participating in, the modeling and verification of leading-edge designs in advanced CMOS processes.

Our modeling engineers are expected to contribute in all of the following areas

• Reading schematics, netlists and circuit specifications to define what each model must capture
• Developing model architecture and accuracy targets, balancing fidelity against simulation speed
• Writing behavioral System Verilog models of analog blocks
• Debugging simulation failures and finding the root cause in the model, RTL or testbench
• Documenting model behavior, limitations and interfaces

Experience And Education

• Hands-on experience writing behavioral models of analog circuits in System Verilog.
• Working knowledge of analog and mixed-signal circuit fundamentals and of the System Verilog UVM methodology, with proven skill debugging failures in simulation and waveforms.
• Familiarity with high-speed interface standards is a plus.