Senior ASIC Verification Engineer (SystemVerilog/UVM)

Broadcom, Inc.; San Jose (CA); On-site; USD 150,000 - 210,000; Full time

Benefits offered by this job

Equity grants

Annual bonus

401(k) with company match

Employee Stock Purchase Program (ESPP)

Job summary

Broadcom, Inc. in San Jose, CA, is seeking experienced ASIC verification engineers to join a high-performance design team.

You will work on state-of-the-art subsystem development, focusing on verification environments, UVM agents, and behavioral models to meet stringent customer requirements. The role emphasizes SystemVerilog verification, DV methodologies, and strong debugging skills, with collaboration across interfaces to design teams and verification teams.

Qualifications

• Bachelor’s degree in Electrical or Computer Engineering, or equivalent.
• 12+ years of relevant industry experience.
• Fluent knowledge of RTL verification methodologies including SystemVerilog.
• Strong experience in ASIC design verification flows and DV methodologies.
• Strong working knowledge of OVM/UVM, C/C++, Perl, and scripting.
• Excellent debugging and independent problem-solving abilities.
• Strong verbal and written communication skills and teamwork.

Responsibilities

• Verification environment development using SystemVerilog and UVM.
• Designing verification components such as UVM agents and behavioral models.
• Implementing coverage and assertions using SystemVerilog.
• Developing random and directed test cases against the specification.
• Analyzing and debugging simulation failures and coverage results.

Skills

SystemVerilog

UVM

RTL verification

C/C++

Perl

Scripting

OVM

Debugging

Communication

Education

Bachelor's degree in Electrical/Computer Engineering

Tools

Emulators

FPGA prototyping

DV tools

Job description

Broadcom, Inc. in San Jose, CA, is seeking experienced ASIC verification engineers to join a high-performance design team.

You will work on state-of-the-art subsystem development, focusing on verification environments, UVM agents, and behavioral models to meet stringent customer requirements. The role emphasizes SystemVerilog verification, DV methodologies, and strong debugging skills, with collaboration across interfaces to design teams and verification teams.