ASIC/RTL Design Engineer 5

TekWissen ®; San Jose (CA); Presencial; USD 120.000 - 190.000; Jornada completa

Descripción de la vacante

TekWissen is seeking a modeling engineer to create behavioral models of analog and mixed-signal circuits in SystemVerilog, integrated into a UVM verification environment for high-speed SerDes and SoC IP.

You will collaborate with analog, RTL and verification teams, reading schematics and netlists, balancing fidelity with speed, debugging failures, and documenting interfaces.

Formación

• Hands-on experience writing behavioral models of analog circuits in SystemVerilog.
• Knowledge of analog and mixed-signal basics and SystemVerilog UVM; strong debugging of simulations and waveforms.
• Familiarity with high-speed interface standards is a plus.

Responsabilidades

• Model and verify leading-edge analog/mixed-signal designs in SystemVerilog.
• Read schematics, netlists and circuit specs to define model scope.
• Develop model architecture and balance fidelity with simulation speed.
• Debug simulation failures and identify root causes in model, RTL or testbench.
• Document model behavior, limitations and interfaces.

Conocimientos

SystemVerilog

Analog/mixed-signal fundamentals

UVM methodology

Debugging simulations

Herramientas

SystemVerilog

UVM

Descripción del empleo

TekWissen is a global workforce management provider headquartered in Ann Arbor, Michigan that offers strategic talent solutions to our clients world-wide. This Client is an American multinational semiconductor company based in Santa Clara, California, that develops computer processors and related technologies for business and consumer markets. Global company that specializes in manufacturing semiconductor devices used in computer processing. The company also produces flash memories, graphics processors, motherboard chip sets, and a variety of components used in consumer electronics goods.

Job Description:

• You will build behavioral models of analog and mixed-signal circuits (PLLs, clocking, ADC/DAC, TX/RX analog front ends, calibration loops) in SystemVerilog.
• Those models drop into a SystemVerilog UVM verification environment used for high-speed SerDes and SoC IP.
• You will work closely with analog circuit designers, RTL designers and verification engineers.
• Successful candidates will be responsible for leading, and participating in, the modeling and verification of leading-edge designs in advanced CMOS processes.
• Our modeling engineers are expected to contribute in all of the following areas:
• Reading schematics, netlists and circuit specifications to define what each model must capture.
• Developing model architecture and accuracy targets, balancing fidelity against simulation speed.
• Writing behavioral SystemVerilog models of analog blocks.
• Debugging simulation failures and finding the root cause in the model, RTL or testbench.
• Documenting model behavior, limitations and interfaces.

Experience and Education:

• Hands-on experience writing behavioral models of analog circuits in SystemVerilog.
• Working knowledge of analog and mixed-signal circuit fundamentals and of the SystemVerilog UVM methodology, with proven skill debugging failures in simulation and waveforms.
• Familiarity with high-speed interface standards is a plus.

TekWissen Group is an equal opportunity employer supporting workforce diversity.