Onsite Analog/Mixed-Signal Modeling Engineer (SystemVerilog)

Dexian; Santa Clara (CA); On-site; USD 110,000 - 117,000; Full time

Job summary

Dexian in San Jose, CA is seeking an Analog/Mixed-Signal Modeling Engineer for a 12+ month onsite assignment. You will develop SystemVerilog analog models and validate simulations in close collaboration with RTL and analog teams.

The role requires SystemVerilog, UVM, RTL coding, and analog/mixed-signal modeling experience; PLL, ADC/DAC, SerDes, VCS, LTspice, and HSPICE familiarity is preferred. This position offers hands-on design exposure in a fast-growing tech staffing environment.

Qualifications

• SystemVerilog, UVM and RTL coding required for analog/mixed-signal modeling.
• Experience with PLLs, ADCs/DACs and SerDes is highly desirable.
• Familiarity with SPICE simulators (LTspice, HSPICE) preferred.

Responsibilities

• Develop SystemVerilog analog models and validate simulations across designs.
• Debug failures and collaborate with RTL and analog design teams.
• Support model validation and regression testing in simulation environments.

Skills

SystemVerilog

UVM

RTL coding

Analog/Mixed-Signal modeling

Tools

VCS

LTspice

HSPICE

Job description

Dexian in San Jose, CA is seeking an Analog/Mixed-Signal Modeling Engineer for a 12+ month onsite assignment. You will develop SystemVerilog analog models and validate simulations in close collaboration with RTL and analog teams.

The role requires SystemVerilog, UVM, RTL coding, and analog/mixed-signal modeling experience; PLL, ADC/DAC, SerDes, VCS, LTspice, and HSPICE familiarity is preferred. This position offers hands-on design exposure in a fast-growing tech staffing environment.