ASIC/RTL Design Engineer

Experis; San Jose (CA); Presencial; USD 93.000 - 133.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Fully onsite in San Jose, CA

Collaborative cross‑functional team

Descripción de la vacante

Semiconductor Industry is seeking an ASIC/RTL Design Engineer to join the team onsite in San Jose, CA. The role focuses on creating SystemVerilog behavioral models for analog/mixed-signal circuits within a UVM verification flow, translating schematics to model requirements, and balancing fidelity with speed.

You will debug issues using waveforms and ensure model interfaces align with RTL and testbenches, collaborating with analog, RTL, and verification teams on high‑speed SerDes and SoC IP

Formación

• Hands-on experience writing behavioral models of analog circuits in SystemVerilog.
• Working knowledge of analog and mixed-signal fundamentals and SystemVerilog UVM.
• Proven ability to debug simulation failures using waveforms and trace analysis.
• Ability to read schematics and netlists to define model behavior.
• Familiarity with high-speed interface standards; LTspice/HSPICE desirable.

Responsabilidades

• Build behavioral models of analog circuits in SystemVerilog for UVM environments.
• Translate schematics and circuit specs into model requirements for SerDes and IP verification.
• Define model architecture and balance fidelity with simulation speed.
• Write and validate behavioral models of analog blocks against transistor-level results.
• Debug simulation failures across model, RTL, and testbench; document interfaces.

Conocimientos

Analog SV modeling

SystemVerilog UVM

Waveform debugging

Schematics/netlists reading

High-speed interfaces

LTSpice/HSPICE familiarity

Herramientas

LTspice

HSPICE

VCS

Descripción del empleo

Our client, Semiconductor Industry is seeking a ASIC/RTL Design Engineer to join their team. As a ASIC/RTL Design Engineer, you will be part of the supporting. The ideal candidate will have strong SystemVerilog modeling skills, proven experience debugging simulation issues, and the ability to collaborate across analog, RTL, and verification teams to deliver leading-edge designs.

Job Title

ASIC/RTL Design Engineer

Location

Onsite to San Jose, CA - 95124

Pay Range

$82 o W2

What's the Job?

• Build behavioral models of analog and mixed-signal circuits (PLLs, clocking, ADC/DAC, TX/RX analog front ends, calibration loops) in SystemVerilog for use in a SystemVerilog UVM verification environment.
• Translate schematics, netlists, and circuit specifications into model requirements that accurately capture the behavior needed for high-speed SerDes and SoC IP verification.
• Develop model architecture and define accuracy targets, balancing fidelity against simulation speed to meet verification goals.
• Write and integrate behavioral SystemVerilog models of analog blocks, then validate model behavior against transistor-level simulation results.
• Debug simulation failures by identifying root causes across the model, RTL, and testbench, and document model behavior, limitations, and interfaces.

What's Needed?

• Hands-on experience writing behavioral models of analog circuits in SystemVerilog.
• Working knowledge of analog and mixed-signal circuit fundamentals and SystemVerilog UVM methodology.
• Proven ability to debug simulation failures using waveforms and trace analysis to determine whether issues originate in the model, RTL, or testbench.
• Experience reading and interpreting schematics, netlists, and circuit specifications to define what each model must capture.
• Familiarity with high-speed interface standards is a plus; experience with VCS and LTSPICE and/or HSPICE simulation is desired.

What's in it for me?

• Work fully onsite in San Jose, CA on leading-edge advanced CMOS designs.
• Collaborate closely with analog circuit designers, RTL designers, and verification engineers to improve model quality and verification throughput.
• Contribute across modeling and verification—from requirements and architecture through validation, debugging, and documentation.
• Build models that directly support UVM verification for high-speed SerDes and SoC IP.
• Join a team where your modeling accuracy, simulation debugging, and technical documentation directly impact product readiness.

Upon Completion Of Waiting Period Consultants Are Eligible For

• Medical and Prescription Drug Plans
• Dental Plan
• Vision Plan
• Health Savings Account
• Health Flexible Spending Account
• Dependent Care Flexible Spending Account
• Supplemental Life Insurance
• Short Term and Long Term Disability Insurance
• Business Travel Insurance
• 401(k), Plus Match
• Weekly Pay