Analog Design Engineer

TekWissen ®; Santa Clara (CA); Presencial; USD 120 000 - 180 000; Tempo integral

Resumo da oferta

TekWissen® Group is seeking an experienced Analog Circuit Design Engineer to work on FinFET-based PLLs and related blocks in a fast-paced semiconductor environment. The role requires hands-on design, verification flows, and close collaboration with layout and test teams to ensure robust, high-yield silicon.

You will design PLL building blocks, run pre-tapeout verifications, and help define production test plans with post-silicon characterization groups. 3–5 years of relevant experience preferred.

Qualificações

• Solid knowledge Analog Circuit Design in FinFET technology, PLLs and subblocks.
• Good knowledge in Physical design, STA, scripting (Tcl), Perl, Python.
• Quality-oriented mindset and strong communication.
• 3–5 years of professional semiconductor experience.

Responsabilidades

• Help design building blocks of a PLL.
• Run pre-tapeout verification to confirm performance, power, reliability and timing.
• Work with layout to deliver the physical design and define production/test plans with post-silicon characterization groups.

Conhecimentos

Analog Circuit Design

FinFET Technology

Cadence ADE-L/ADE-XL

Scripting (Python, Perl)

Physical Design & STA

Team Collaboration

Formação académica

Master's or Bachelor's degree in Electrical Engineering

Ferramentas

Cadence Tools (ADE-L/ADE-XL)

Spectre/HSPICE

MATLAB

SystemVerilog

Calibre/ICV (layout verification)

Descrição da oferta de emprego

TekWissen is a global workforce management provider headquartered in Ann Arbor, Michigan that offers strategic talent solutions to our clients worldwide

JOB Description:

THE PERSON:

• Solid knowledge Analog Circuit Design in FinFET technology specifically in PLLs and associated subblocks including VCO, charge-pump, dividers, state machines, LDO, feedback and compensation techniques, bandgap, TDC, interpolator circuits, high speed buffers etc.
• Solid knowledge of industry standard tools and practices for analog circuit design
• Good knowledge in Physical design, STA, methodology scripts (Tcl), knowledge on Perl, Python
• Quality-oriented mindset
• Strong and effective communication skills and team spirit

KEY RESPONSIBILITIES:

• Help design of building blocks of a PLL
• Run pre-tapeout verification flows to confirm design meets performance, power, reliability and timing requirements.
• Work closely with layout engineers to deliver the physical design as well as define production/bench-level test plans with post-silicon characterization groups for silicon evaluation to ensure interlocked and high-quality execution

PREFERRED EXPERIENCE:

• 3-5 years of professional experience in the semiconductor industry
• Experience in FinFET & Dual Patterning nodes such as 16/14/10/7nm/5nm
• Hands-on design experience in performance analog and hybrid Phase Locked Loops, analog-to-digital (ADC), digital-to-analog (DAC) data converter, VCO, LDO, bandgap, charge pump, op-amps, interpolator circuits.
• Experience with the following is a plus: Digital PLL techniques, TDC or DSP and control theory experience related to digital PLLs, Dual charge-pump PLL designs, Fractional-N PLLs, spread-spectrum PLLs.
• Proficient with Cadence custom circuit design tools like ADE-L and ADE-XL and running Monte-Carlo, noise, aging, EM and IR drop simulations and stability analysis. Helic/EMX is a plus.
• Have good experience with simulation tools such as Spectre, Hspice, AFS, and MATLAB, System Verilog, Python.
• Capable of understanding DRC and LVS results with verification tools (Calibre, ICV, or like)
• Proficiency in scripting languages like Perl, Python, matlab etc. is a plus.
• Able to work effectively in a team, with good interpersonal skills, enthusiasm and positive energy
• Possess strong analytical/problem solving skills and pronounced attention to details
• Must be a self-starter, and able to independently drive tasks to completion

ACADEMIC CREDENTIALS:

• Master’s or Bachelor's degree in electrical engineering or equivalent required

TekWissen® Group is an equal opportunity employer supporting workforce diversity.