Mixed Signal Verification Engineer

Prodapt ASIC services (Formerly Innovative Logic); San Jose (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

Prodapt ASIC Services (formerly Innovative Logic) in San Jose, CA seeks a Senior Mixed Signal Verification Engineer to join our on-site team. You will develop and verify AMS/DMS testbenches for wireless RF and high-speed PHY, and collaborate with RF/Analog design engineers to model analog circuits.

The role requires a BS/BE in engineering, 3+ years of experience, and strong skills in Verilog/SystemVerilog, UVM, and digital/VLSI simulation.

Qualifications

• BS or BE in EE/CS required.
• 3+ years of experience.
• Strong digital VLSI simulation flow.
• Experience with mixed-mode and analog simulation.
• Proficiency in Verilog/SystemVerilog and RNM modeling.
• Experience with digital verification, UVM, and waveform debugging.
• Excellent communication and interpersonal skills; teamwork.
• Knowledge of RF transceiver and Serdes PHY is preferred.

Responsibilities

• Create AMS/DMS testbenches for wireless RF and high-speed PHY.
• Collaborate with RF/Analog design engineers on analog models.
• Support silicon bring-up and commercialization.

Skills

Mixed-signal verification

Verilog/SystemVerilog

UVM

RF/Analog modeling

Digital VLSI simulation

Serdes PHY

RNM modeling

Teamwork & communication

Education

BS or BE in EE/CS

Job description

Prodapt ASIC Services (formerly Innovative Logic) provides end-to-end SoC/ASIC, FPGA, and embedded software solutions. Our design services cover the complete lifecycle from RTL to GDSII, covering domains like 3nm node physical design, UVM verification, DFT, and silicon bring-up for 5G, AI, and IoT.

We are looking for Senior Mixed Signal Verification Engineer in San Jose, CA and its a 5 day onsite position

Job Responsibilities:

• Creating AMS/DMS testbench for wireless RF and High Speed PHY.
• Working with RF/Analog design engineers for analog circuit models
• Support silicon bring-up and commercialization.

Required Skills:

• BS or BE minimum, 3+ year experiences
• Deep understanding of digital VLSI simulation flow
• Deep understanding of mixed-mode and analog simulation flow
• Experience with Verilog/SystemVerilog and RNM modeling
• Experience with digital verification, UVM, and waveform debug
• Teamwork, dedication, strong communications and interpersonal skills
• Excellent communication skills both written and verbal PREFERED SKILLS
• Deep understanding of wireless RF transceiver and Serdes PHY technology