ASIC Package Eng Intern/Co-op — Design & Yield

Advanced Micro Devices, Inc.; Town of Fishkill (NY); Hybrid; USD 34,000 - 52,000; Full time

Job summary

AMD invites you to join our ASIC Packaging team as a co-op/intern, working 40 hours a week in a hybrid or onsite structure. You will contribute to substrate, interposer and bump designs, support design verification, and help improve yield through data analytics and material benchmarking.

This role offers exposure to next-gen packaging tech, collaboration with engineers, and hands-on project experience in a dynamic semiconductor environment.

Qualifications

• Enrolled in a US university pursuing a Bachelor's degree in EE or related field.
• Coursework related to transmission lines and electric circuits.
• Familiar with package, silicon or PCB design software.
• Scripting experience with Perl, Python or SQL.
• Knowledge of data analytics and Power BI.

Responsibilities

• Support Package Design and Package Development Engineers in prioritizing and optimizing new projects.
• Assist substrate, interposer and bump designs for AMD products, test vehicles and probe cards.
• Contribute to design verification to ensure performance, quality and efficiency.
• Analyze yield and defect metrics to improve design performance.
• Benchmark packaging materials and interact with partners for cost-efficient designs.

Skills

ASIC packaging

Substrate design

Python scripting

Data analytics

Power BI

PCB design

Education

Bachelor's degree in Electrical Engineering

Engineering Science

Computer Engineering

Material Science Engineering

Tools

Package design software

Semiconductor modeling tools

Job description

AMD invites you to join our ASIC Packaging team as a co-op/intern, working 40 hours a week in a hybrid or onsite structure. You will contribute to substrate, interposer and bump designs, support design verification, and help improve yield through data analytics and material benchmarking.

This role offers exposure to next-gen packaging tech, collaboration with engineers, and hands-on project experience in a dynamic semiconductor environment.