ASIC DFT/DV Verification Lead - Hybrid (San Jose)

Cisco; San Jose (CA); Hybrid; USD 187,000 - 268,000; Full time

Job summary

Cisco's Silicon One team in San Jose seeks a DFT Verification Lead to drive test planning and develop robust test benches for comprehensive DFT validation across silicon stages. You will collaborate with Front-end RTL and backend PD teams to ensure high-quality test coverage.

The role requires strong SystemVerilog, DVE/Verdi debugging, and TCL/Python/Perl scripting skills, with a focus on scalable DFT solutions for new silicon devices.

Qualifications

• Bachelor's degree with 8+ years of related experience, or Master's with 6+ years, or PhD with 3+ years.
• Experience in test planning based on complex design specifications.
• Proficient in testbench development using SystemVerilog (SV).
• Experience debugging using DVE/Verdi.
• Familiarity with TCL, Python or Perl.

Responsibilities

• Plan and develop test benches to verify DFT architecture supporting ATE screening, in-system test, and debug needs.
• Collaborate with design, verification and PD teams to integrate test logic across implementation and post-silicon validation flows.
• Lead DFT verification efforts for new silicon models and die configurations with minimal mentorship.

Skills

Test planning

SystemVerilog

DVE/Verdi

TCL

Python/Perl

Education

Bachelor's degree

Master's degree

PhD

Tools

UVM

JTAG MBIST

Job description

Cisco's Silicon One team in San Jose seeks a DFT Verification Lead to drive test planning and develop robust test benches for comprehensive DFT validation across silicon stages. You will collaborate with Front-end RTL and backend PD teams to ensure high-quality test coverage.

The role requires strong SystemVerilog, DVE/Verdi debugging, and TCL/Python/Perl scripting skills, with a focus on scalable DFT solutions for new silicon devices.