Senior ASIC RTL Engineer for DFT & High-Perf Silicon

Anysilicon; San Jose (CA); On-site; USD 170,000 - 250,000; Full time

Job summary

Cisco's Silicon One team in California is recruiting a Senior RTL/DFT engineer to design robust DFT RTL and ensure high-performance silicon. You will work with front-end RTL and backend physical design to translate architecture into reliable testable silicon.

The role requires 7+ years in electrical or computer engineering, a strong background in Verilog/SystemVerilog, and experience with DFT/MBIST, UPF power intent, and industry interfaces.

Qualifications

• Bachelor's or Master's Degree in Electrical or Computer Engineering.

Responsibilities

• Collaborate with Front-end RTL and backend physical design teams to understand chip architecture.
• Drive high-quality Design for Test (DFT) RTL for silicon solutions.
• Ensure silicon solutions meet Cisco’s standards for performance and innovation.
• Participate in cross-functional teamwork to deliver advanced networking silicon.

Skills

Verilog/SystemVerilog

Verilog simulators

linting

CDC checkers

synthesis

formal verification

AMBA protocol

JTAG protocol

memory interfaces

Power optimization

UPF power intent

DFT/MBIST

post-silicon debug

Education

Bachelor's or Master's Degree in Electrical or Computer Engineering

Job description

Cisco's Silicon One team in California is recruiting a Senior RTL/DFT engineer to design robust DFT RTL and ensure high-performance silicon. You will work with front-end RTL and backend physical design to translate architecture into reliable testable silicon.

The role requires 7+ years in electrical or computer engineering, a strong background in Verilog/SystemVerilog, and experience with DFT/MBIST, UPF power intent, and industry interfaces.