Senior ASIC DFT & DV Engineer (Hybrid – San Jose)

Cisco; San Jose (CA); Hybrid; USD 168,000 - 245,000; Full time

Job summary

Cisco is seeking an experienced DFT/Test Engineer for the Silicon One team in San Jose. You will contribute to thorough test planning, develop test benches, and own MBIST methodology to ensure high-quality memory testing across large silicon designs.

Collaborate with RTL and physical design teams to strengthen DFT verification, while advancing design-for-test capabilities in a hybrid work environment with three days on-site.

Qualifications

• Bachelor’s in Electrical Engineering or equivalent with 7+ years (or Master’s with 4+ years) of experience.
• Prior experience in test planning based on complex design specification
• Experience debugging using DVE/Verdi.
• Prior experience with memory architectures (SRAM, DRAM, etc.) and failure modes.
• Experience with TCL, Python or Perl.

Responsibilities

• Responsible for thorough test planning and development of test benches to verify comprehensive Design-for-Test (DFT) architecture that supports ATE screening, in-system test, debug and diagnostics needs of the design.
• Own the MBIST methodology across the Silicon One portfolio, driving unified, high-quality standards for memory testing.
• Architect reusable, hierarchical infrastructures that scale across massive designs to accelerate time-to-market for future silicon.
• Work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive high-quality DFT verification.

Skills

DVE/Verdi debugging

Test planning

Memory architectures

Scripting (TCL/Python/Perl)

Education

Bachelor's in Electrical Engineering or equivalent

Master's in Electrical Engineering or related field

Tools

Synopsys DesignWare

SMS

TestMax

Mentor Graphics Tessent

Verilog

SV (SystemVerilog)

Job description

Cisco is seeking an experienced DFT/Test Engineer for the Silicon One team in San Jose. You will contribute to thorough test planning, develop test benches, and own MBIST methodology to ensure high-quality memory testing across large silicon designs.

Collaborate with RTL and physical design teams to strengthen DFT verification, while advancing design-for-test capabilities in a hybrid work environment with three days on-site.