ASIC DFT Engineer II Full Time – United States

Anysilicon; San Jose, Northern (CA, KY); Hybrid; USD 120,000 - 160,000; Full time

Job summary

Cisco's Silicon One team seeks an ASIC DFT Engineer II to design for test features across ATE and in-system test, collaborating with design and verification groups to ensure robust test logic integration.

The role emphasizes SystemVerilog-based validation, ATPG methods, and scripting to automate validation workflows, with growing responsibilities in a global engineering environment.

Qualifications

• Master's degree in ASIC Engineering or related field (or Bachelor's with 2 years' experience).
• Foundational understanding of JTAG protocols, scan architectures, and BIST.
• Experience with gate-level simulations and debugging using simulators like VCS.

Responsibilities

• Implement Hardware Design-for-Test (DFT) features for ATE, in-system test, debug, and diagnostics.
• Create and enhance automation scripts for improved implementation efficiency.
• Collaborate with Design, Design Verification, and Physical Design teams for test logic integration and validation.
• Validate test timing and logic equivalency using SystemVerilog.
• Utilize ATPG and EDA tools for test pattern generation and analysis.

Skills

SystemVerilog

Logic equivalence checking

VLSI timing concepts

Post-silicon validation

Communication skills

Education

Master's degree

Bachelor's degree

Tools

VCS

ATPG tools

EDA tools

Job description

ASIC DFT Engineer II Full Time – United States

Cisco's Silicon One team is seeking potential candidates for the role of ASIC Design for Test Engineer, focusing on Design-for-Test (DFT) within innovative hardware platforms that drive core Switching, Routing, and Wireless products. This role emphasizes collaboration and creativity in a global team environment, contributing to the future of technology in the AI era.

Responsibilities:

• Implement Hardware Design-for-Test (DFT) features for ATE, in-system test, debug, and diagnostics.
• Create and enhance automation scripts for improved implementation efficiency.
• Collaborate with Design, Design Verification, and Physical Design teams for test logic integration and validation.
• Validate test timing and logic equivalency using SystemVerilog.
• Utilize ATPG and EDA tools for test pattern generation and analysis.

Qualifications:

• Master's degree with 0 years of experience or Bachelor's degree with 2 years of experience in ASIC Engineering or related field.
• Foundational understanding of JTAG protocols, scan architectures, and Built-In Self-Test (BIST).
• Familiarity with EDA and ATPG tools, and scripting skills in Python, Tcl, or Perl.
• Experience with gate-level simulations and debugging using simulators like VCS.

Skills:

• Practical experience in verification skills, including SystemVerilog and logic equivalency checking.
• Understanding of VLSI circuit behaviors and basic timing concepts.
• Exposure to post-silicon validation using DFT patterns and Test Static Timing Analysis.
• Strong verbal and written communication skills for effective collaboration.

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• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

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