ASIC Design Verification Engineer [Santa Clara, CA]

Anysilicon; Austin, Northern (TX, KY); Hybrid; USD 110,000 - 160,000; Full time

Job summary

Qualcomm Technologies, Inc. in Austin seeks an ASIC Design Verification Engineer to lead verification across the lifecycle, from concept to post-silicon support, focusing on digital power IPs and advanced verification methodologies.

Responsibilities include pre-silicon test plan development, testbenches with SystemVerilog/UVM, coverage and assertion modeling, formal verification, UPF power-aware techniques, and process automation to boost efficiency.

Qualifications

• Bachelor’s degree in science or engineering with relevant verification experience.
• 3+ years of design verification experience using UVM and assertion-based tech.
• Experience verifying complex SOCs or SOC subsystems.

Responsibilities

• Manage verification lifecycle from concept through tape-out and post-silicon support.
• Develop pre-silicon test plans for digital power IPs.
• Create testbenches using SystemVerilog/UVM and develop coverage models.
• Develop assertion models and apply formal verification techniques.
• Apply power-aware UPF verification methodologies.
• Automate verification processes to improve efficiency.

Skills

UVM

SystemVerilog

Assertions

C++

Python

DDR

SOC technologies

Memory verification VIPs

DDR PHY

Firmware/Driver development

Formal verification

Education

Bachelor's degree in Science or Engineering

Tools

DDR VIPs

DDR PHY

Job description

Qualcomm Technologies, Inc. is seeking an ASIC Design Verification Engineer to join its Engineering Group, specifically within ASICS Engineering. This role is pivotal in the verification lifecycle, from system-level concept to post-silicon support, focusing on digital power IPs and utilizing advanced verification methodologies.

Responsibilities:

• Manage the complete verification lifecycle from concept to tape out and post-silicon support.
• Develop comprehensive pre-silicon test plans for digital power IPs.
• Create testbenches using SystemVerilog-UVM and develop coverage and assertion models.
• Implement formal verification techniques for property checking.
• Learn and apply power-aware UPF verification methodologies.
• Automate processes to enhance verification efficiency.

Qualifications:

• Bachelor's degree in Science, Engineering, or related field with 2+ years of relevant experience; or a Master's degree with 1+ year; or a PhD in a related field.
• Minimum 3 years of experience in design verification using UVM and assertion-based technologies.
• Experience in verifying complex SOCs or SOC subsystems.

Skills:

• Proficiency in UVM, SystemVerilog, assertions, C++, and Python.
• Familiarity with DDR, CACHE, and SOC technologies.
• Experience with memory verification VIPs and DDR PHY.
• Exposure to firmware/driver development and formal verification techniques.