Sr Design and Verification Engineer

Chiparama; San Jose (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

Chiparama in California seeks a Design Verification Engineer with strong ASIC/SoC verification experience to develop verification environments and ensure high-quality digital designs.

You will build testbenches in SystemVerilog/UVM, create constrained-random tests, analyze coverage, and debug RTL with design teams. Familiarity with AMBA/AXI, PCIe, Ethernet is a plus; scripting with Python/Perl is beneficial.

Qualifications

• Must have SystemVerilog/UVM experience in verification.
• Solid RTL and digital design understanding for ASIC/SoC verification.
• Experience with simulation tools (VCS/Xcelium/Questa) and debugging.

Responsibilities

• Develop verification environments and testbenches using SystemVerilog/UVM.
• Create and run functional, regression, and constrained-random tests.
• Analyze functional/code coverage and drive coverage closure.
• Debug RTL and simulation issues with design teams.
• Verify protocols like AMBA/AXI, PCIe, Ethernet or similar interfaces.
• Automate testing and regression using scripting (Python/Perl/Shell).

Skills

SystemVerilog & UVM

RTL & digital design

Debugging & scripting

Education

Bachelor's/Master's degree in EE/EC/CS

Tools

VCS

Xcelium

Questa

Job description

Job Title: Design Verification Engineer _ ( with Direct Client )

We are looking for a Design Verification Engineer with strong experience in ASIC/SoC verification to develop and execute verification environments and ensure high-quality digital designs.

Responsibilities

• Develop verification environments and testbenches using SystemVerilog and UVM.
• Create and execute functional, regression, and constrained-random tests.
• Analyze functional/code coverage and drive coverage closure.
• Debug RTL and simulation failures and work with design teams to resolve issues.
• Verify protocols such as AMBA/AXI, PCIe, Ethernet, or similar interfaces.
• Automate testing and regression using Python, Perl, or Shell scripting.

Required Skills

• Strong SystemVerilog & UVM experience.
• Solid understanding of RTL, digital design, and ASIC/SoC verification.
• Experience with simulation tools such as VCS, Xcelium, or Questa.
• Strong debugging and scripting skills.
• Bachelor's/Master's degree in Electrical, Electronics, or Computer Engineering.