Senior ASIC Verification Engineer – SystemVerilog/UVM

Socket.dev

San Diego (CA)

On-site

USD 116,000 - 173,000

Full time

10 days ago

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Job summary

Qualcomm Technologies, Inc. in San Diego seeks a verification engineer to contribute to the full pre-silicon verification lifecycle for digital power IPs. You will design testplans, build advanced testbenches, and work with SystemVerilog-UVM, coverage, and formal verification.

Responsibilities include developing block-level test environments, automating verification flows, and ensuring robust validation prior to tape-out. A strong background in ASIC design/verification and C/C++ is preferred.

Qualifications

  • Bachelor's degree in Science, Engineering, or related field required with 2+ years ASIC design/verification experience.
  • Master's degree in Science, Engineering, or related field with 1+ year experience is desirable.
  • PhD in Science, Engineering, or related field is considered.

Responsibilities

  • Perform pre-silicon test planning for digital power IPs.
  • Develop testbenches using SystemVerilog-UVM and coverage.
  • Create assertion models and apply formal verification.
  • Develop automation to improve verification efficiency.

Skills

ASIC design
SystemVerilog
Verilog
UVM
C/C++ programming
Scripting: Python/Perl
Formal verification
AMBA AXI/ARB

Education

Bachelor's degree in Science/Engineering or related field
Master's degree in Science/Engineering or related field
PhD in Science/Engineering or related field

Tools

SystemVerilog
UVM
Verilog
VHDL
Formal verification tools

Job description

Qualcomm Technologies, Inc. in San Diego seeks a verification engineer to contribute to the full pre-silicon verification lifecycle for digital power IPs. You will design testplans, build advanced testbenches, and work with SystemVerilog-UVM, coverage, and formal verification.

Responsibilities include developing block-level test environments, automating verification flows, and ensuring robust validation prior to tape-out. A strong background in ASIC design/verification and C/C++ is preferred.

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