ASIC Verification Engineer – Digital Power, UVM & Formal

Anysilicon; Austin, Northern (TX, KY); Hybrid; USD 110,000 - 160,000; Full time

Job summary

Qualcomm Technologies, Inc. in Austin seeks an ASIC Design Verification Engineer to lead verification across the lifecycle, from concept to post-silicon support, focusing on digital power IPs and advanced verification methodologies.

Responsibilities include pre-silicon test plan development, testbenches with SystemVerilog/UVM, coverage and assertion modeling, formal verification, UPF power-aware techniques, and process automation to boost efficiency.

Qualifications

• Bachelor’s degree in science or engineering with relevant verification experience.
• 3+ years of design verification experience using UVM and assertion-based tech.
• Experience verifying complex SOCs or SOC subsystems.

Responsibilities

• Manage verification lifecycle from concept through tape-out and post-silicon support.
• Develop pre-silicon test plans for digital power IPs.
• Create testbenches using SystemVerilog/UVM and develop coverage models.
• Develop assertion models and apply formal verification techniques.
• Apply power-aware UPF verification methodologies.
• Automate verification processes to improve efficiency.

Skills

UVM

SystemVerilog

Assertions

C++

Python

DDR

SOC technologies

Memory verification VIPs

DDR PHY

Firmware/Driver development

Formal verification

Education

Bachelor's degree in Science or Engineering

Tools

DDR VIPs

DDR PHY

Job description

Qualcomm Technologies, Inc. in Austin seeks an ASIC Design Verification Engineer to lead verification across the lifecycle, from concept to post-silicon support, focusing on digital power IPs and advanced verification methodologies.

Responsibilities include pre-silicon test plan development, testbenches with SystemVerilog/UVM, coverage and assertion modeling, formal verification, UPF power-aware techniques, and process automation to boost efficiency.