Senior ASIC Engineer

Anysilicon; Santa Clara (CA); Hybrid; USD 120,000 - 170,000; Full time

Job summary

Qualcomm Atheros, Inc. is seeking an experienced ASIC Verification Engineer to join the ASICS Engineering group.

The role focuses on owning block-level verification for wireless connectivity designs, developing verification strategies, and ensuring high-quality integration and testing across cross-functional teams. Responsibilities include owning verification coverage, building UVM test-benches, and coordinating with IP teams to create thorough test plans.

Qualifications

• Bachelor’s degree in Science, Engineering or related field with 2+ years of relevant experience, or Master/PhD.
• 2+ years of ASIC verification experience.
• 1+ year of experience with UVM.

Responsibilities

• Own block-level verification for wireless connectivity designs and meet coverage goals.
• Develop and maintain test-bench, coding guidelines, and best practices for UVM test-benches.
• Create a comprehensive verification strategy that includes simulations, formal verification, and HW/SW reuse.
• Collaborate with cross-functional IP teams for integration verification.
• Work with the design team to understand specifications and develop a comprehensive test plan for quality verification.

Skills

Scripting languages

UVM from scratch

Digital logic & SoC architecture

Low-power verification (GLS)

Testbench automation & bug tracking

Problem-solving & teamwork

Education

Bachelor’s degree in Science/Engineering or related field (2+ yrs)

Tools

UVM framework

Job description

Qualcomm Atheros, Inc. is seeking an experienced ASIC Verification Engineer to join their Engineering Group, specifically within ASICS Engineering. The role involves owning block-level verification for wireless connectivity designs, developing comprehensive verification strategies, and collaborating with cross-functional teams to ensure high-quality integration and testing.

Responsibilities:

• Own block level verification for wireless connectivity designs and meet coverage goals.
• Develop and maintain test-bench, coding guidelines, and best practices for UVM test-benches.
• Create a comprehensive verification strategy that includes simulations, formal verification, and HW/SW reuse.
• Collaborate with cross-functional IP teams for integration verification.
• Work with the design team to understand specifications and develop a comprehensive test plan for quality verification.

Qualifications:

• Bachelor's degree in Science, Engineering, or related field with 2+ years of relevant experience; OR a Master's degree with 1+ year of experience; OR a PhD in a related field.
• 2+ years of ASIC Verification experience.
• 1+ year of experience working with UVM.

Skills:

• Proficiency in scripting languages.
• Experience building at least one test bench using UVM from scratch.
• Strong understanding of digital logic design techniques and SoC architecture, including ARM CPUs and AMBA bus protocols (AHB, AXI).
• Knowledge of low power processor verification and GLS flows is a plus.
• Experience with testbench automation and industry-standard bug tracking.
• Strong problem-solving skills and ability to work collaboratively in a team environment.