Engineer|13083 Engineer|13083

ALTEN; San Diego (CA); On-site; USD 100,000 - 140,000; Full time

Job summary

ALTEN is seeking a talented engineer to join Qualcomm's design verification team in San Diego, California. In this role, you will be responsible for verifying high-speed mixed-signal IP designs for products aimed at 5G, AI, IoT, and automotive applications.

Your responsibilities include defining and implementing test plans, developing testbenches, and working closely with design teams. The ideal candidate will hold a Master's or Bachelor's degree in Electrical Engineering and possess at least 2 years of relevant experience with ASIC design verification.

Qualifications

• At least 2 years of ASIC design verification or related work experience.
• Knowledge of a HVL methodology such as SystemVerilog/UVM.
• Experience with ASIC simulation/formal tools.

Responsibilities

• Define pre-silicon and post-silicon test plans based on design specs.
• Architect and develop the testbench using advanced verification methodology.
• Implement power-aware verification methodology in SV/UVM environment.
• Author assertions in SVA, develop test cases and coverage models.

Skills

SystemVerilog/UVM

ASIC design verification

Analog/mixed-signal simulation

Power-aware verification

Scripting (Python or Perl)

Education

Master's or Bachelor's degree in Electrical Engineering

Tools

VCS

Xcellium/NCsim

Modelsim/Questa

Job description

Join Qualcomm's design verification team in verifying the high-speed mixed-signal IP designs (PCIe, USB, MIPI, CXL, C2C, D2D, DDR, PLL, DAC, Client, Sensors, etc.) for exciting products targeted for 5G, AI/Client, compute, IOT, and automotive applications. The team is responsible for the complete design verification lifecycle, from system‑level concept to tape out and post‑silicon support.

Responsibilities

• Define pre‑silicon and post‑silicon test plans based on design specs and using applicable standards while working closely with the design team.
• Architect and develop the testbench using advanced verification methodology such as SystemVerilog/UVM, analog/mixed‑signal simulation, low‑power verification, formal verification, and gate‑level simulation to ensure high design quality.
• Implement power‑aware verification methodology in SV/UVM environment to support coverage and assertions.
• Author assertions in SVA, develop test cases and coverage models, debug, and ensure coverage closure.
• Work with digital design, analog circuit design, modeling, controller/subsystem, and SoC integration teams to complete successful PHY‑level verification, integration into subsystem and SoC, and post‑silicon validation.

Minimum Qualifications

• Master's or Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field.
• At least 2 years of ASIC design verification or related work experience.
• Knowledge of a HVL methodology such as SystemVerilog/UVM.
• Experience with various ASIC simulation/formal tools such as VCS, Xcellium/NCsim, Modelsim/Questa, VCFormal, Jaspergold, or similar.

Preferred Qualifications

• Experience with low‑power design verification, formal verification, and gate‑level simulation.
• Knowledge of standard protocols such as PCIe, USB, MIPI, LPDDR, etc.
• Experience in scripting languages (Python or Perl).
• Experience with mixed‑signal IP design verification, including USB, PCIe, CXL, C2C, D2D, MIPI, UFS, DDR, PLL, data converters (DAC, Client), or sensors.