ASIC Design Verification Engineer (Santa Clara, CA)

Qualcomm

Santa Clara (CA)

On-site

USD 153,200 - 229,800

Full time

14 days+
Application generator

Don’t send a generic resume — generate a resume and cover letter tailored to this exact role.

Get past ATS filters

Benefits offered by this job

Competitive annual discretionary bonus
RSU grants
Accessible workplace
Support for individuals with disabilities

Job summary

A leading technology company in California is seeking an experienced ASIC Design Verification Engineer to oversee the verification lifecycle for digital power IPs. The ideal candidate will have at least 3 years of experience in verification roles and a Bachelor's degree or higher in related fields. This position offers a competitive salary range of $153,200.00 - $229,800.00 with additional benefits including a discretionary bonus program.

Qualifications

  • Minimum 3 years of DV experience using UVM/assertion-based verification technologies.
  • Experience in verifying complex SOC or SOC subsystems.
  • Exposure to performance and power verification.

Responsibilities

  • Complete verification lifecycle from system-level concept to tape out.
  • Comprehensive pre-silicon test planning for digital power IPs.
  • Develop automation to improve verification efficiency.

Skills

UVM
SystemVerilog
C++
Python

Education

Bachelor's degree in Science, Engineering, or related field
Master's degree in Science, Engineering, or related field
PhD in Science, Engineering, or related field

Job description

Company:
Qualcomm Technologies, Inc.
Job Area:
Engineering Group, Engineering Group > ASICS Engineering
General Summary:

Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. This is the Invention Age - and this is where you come in as an ASIC Design Verification Engineer.

The team is responsible for the complete verification lifecycle, from system-level concept to tape out and post-silicon support. The position involves comprehensive pre-silicon test planning for digital power IPs, testbench development using the advanced verification methodology such as SystemVerilog-UVM, coverage development, assertion model development and formal verification (property checking). The role includes learning and deploying power-aware UPF verification flow and methodology, and developing automation to improve verification efficiency.

Qualifications:
  • Minimum 3 years of DV experience using UVM/assertion-based verification technologies.
  • Experience in verifying complex SOC or SOC subsystems.
  • Experience with caches and DDR memory protocol verification.
  • Experience with using memory verification VIPs.
  • Exposure to DDR phy.
  • Exposure to firmware/driver development using C++.
  • Exposure to multiple successful tapeouts from conception to post-silicon debug.
  • Exposure to formal verification.
  • Exposure to PASIM simulations.
  • Exposure to performance and power verification.

Skill proficiency: UVM, SystemVerilog, assertion, C++, Python.

Technology: DDR, CACHE, SOC.

Minimum Qualifications:
  • Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
  • Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
  • PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accommodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able to participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities.

EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.

Pay range & Other Compensation & Benefits: $153,200.00 - $229,800.00. This pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. In addition, Qualcomm offers a competitive annual discretionary bonus program and RSU grants. For more information about benefits, please visit the US benefits page.

If you would like more information about this role, please contact Qualcomm Careers.

Get your free, confidential resume review.
or drag and drop your file here.
Similar jobs

Similar jobs worth comparing

ASICS Design Verification Engineer-Senior
ASICS Design Verification Engineer-Senior

Socket.dev • San Diego (CA)

On-site
USD 116,000 - 173,000
ASICS Design Verification Engineer-Senior
ASICS Design Verification Engineer-Senior

Qualcomm • San Diego (CA)

On-site
USD 116,000 - 173,000
ASICS Design Verification Engineer
ASICS Design Verification Engineer

Qualcomm • San Diego (CA)

On-site
USD 140,000 - 210,000
Competitive salary
Discretionary bonus program
Annual RSU grants
+1
SOC Verification and Methodology Engineer
SOC Verification and Methodology Engineer

Qualcomm • San Diego (CA)

On-site
USD 164,000 - 246,000
SOC Verification and Methodology Engineer - SCL
SOC Verification and Methodology Engineer - SCL

Qualcomm • San Diego (CA)

On-site
USD 99,000 - 148,000
Mixed Signal Design Verification Engineer
Mixed Signal Design Verification Engineer

Qualcomm • San Diego (CA)

On-site
USD 140,000 - 210,000
GSoC Design Verification Engineer
GSoC Design Verification Engineer

Qualcomm • San Diego (CA)

On-site
USD 99,000 - 148,000
ASICS Design Verification Engineer-Senior San Diego, California, United States of America ASICS Engineering
ASICS Design Verification Engineer-Senior San Diego, California, United States of America ASICS Engineering

Qualcomm • San Diego (CA), Northern (KY)

Hybrid
USD 116,000 - 173,000
Annual discretionary bonus
RSU grants
Competitive benefits package
+1
SOC Design Verification Engineer-Staff
SOC Design Verification Engineer-Staff

Qualcomm • San Diego (CA)

On-site
USD 140,000 - 210,000
Competitive bonus program
RSU grants
Excellent benefits package
SOC Design Verification Engineer
SOC Design Verification Engineer

Qualcomm • San Diego (CA)

On-site
USD 98,500 - 147,700