Senior ASIC Verification Engineer — SystemVerilog/UVM

Qualcomm; San Diego (CA); On-site; USD 116,000 - 173,000; Full time

Job summary

Qualcomm Technologies, Inc. is seeking an experienced engineer to lead pre-silicon verification for digital power IPs. You will craft test benches, develop coverage and assertions, and apply formal verification techniques to ensure robust designs.

The role requires strong SystemVerilog/UVM background, ASIC design/verification experience, and collaboration within the ASICS Engineering group in California. Relocation and benefits are provided as part of Qualcomm's compensation package.

Qualifications

• 2+ years of ASIC design, verification, validation, integration, or related work experience.
• 1+ year of ASIC design, verification, validation, integration, or related work experience (Master's level).
• PhD holders meet qualification requirements.

Responsibilities

• Pre-silicon test planning for digital power IPs and testbench development.
• Develop verification environments and coverage with SystemVerilog, UVM, and assertions.
• Explore formal verification (property checking) and UPF verification flows.

Education

Bachelor's degree in Engineering, Science, or closely related field

Master's degree in Computer Science, Electrical Engineering, or related

PhD in Science, Engineering, or related field

Tools

SystemVerilog-UVM

Job description

Qualcomm Technologies, Inc. is seeking an experienced engineer to lead pre-silicon verification for digital power IPs. You will craft test benches, develop coverage and assertions, and apply formal verification techniques to ensure robust designs.

The role requires strong SystemVerilog/UVM background, ASIC design/verification experience, and collaboration within the ASICS Engineering group in California. Relocation and benefits are provided as part of Qualcomm's compensation package.