ASICS Design Verification Engineer

Qualcomm; San Diego (CA); On-site; USD 140,000 - 210,000; Full time

Benefits offered by this job

Competitive salary

Discretionary bonus program

Annual RSU grants

Comprehensive benefits package

Job summary

A leading technology firm is seeking an experienced engineer in San Diego to manage the complete verification lifecycle for digital power IPs. The ideal candidate has a Bachelor's degree in Engineering or Science and over four years of experience in ASIC design and verification, with proficiency in SystemVerilog and related methodologies. This role offers a competitive salary and dynamic work environment.

Qualifications

• Bachelor's degree in a related field and 4+ years in ASIC design.
• Master's degree and 3+ years or PhD and 2+ years in ASIC work.
• Experience with scripting/automation skills.

Responsibilities

• Manage complete verification lifecycle for digital power IPs.
• Develop testbench using SystemVerilog-UVM and perform coverage development.
• Implement power-aware UPF verification methodology.

Skills

ASIC design and verification methodology

SystemVerilog

Automation scripting

Digital design concepts

C/C++ programming

Education

Bachelor's degree in Engineering, Science, or related field

Master's degree in Computer Science, Electrical Engineering, or related field

Tools

SystemVerilog-UVM

Verification methodologies (UVM, OVM)

Perl

Python

Job description

Overview

Qualcomm Technologies, Inc. – Engineering Group, ASICS Engineering. Qualcomm is a leading technology innovator focused on enabling next-generation experiences and transforming communication and data processing to create a smarter, connected future.

The team is responsible for the complete verification lifecycle, from system-level concept to tape-out and post-silicon support. The position involves comprehensive pre-silicon test planning for digital power IPs, testbench development using SystemVerilog-UVM, coverage development, assertion model development and formal verification (property checking). Learn and deploy power-aware UPF verification flow and methodology. Involve in developing automation to improve verification efficiency.

Responsibilities

• Complete verification lifecycle activities from concept to post-silicon support for digital power IPs.

• Perform pre-silicon test planning, testbench development using SystemVerilog-UVM, coverage development, assertion modeling, and formal verification (property checking).

• Learn and deploy power-aware UPF verification flow and methodology.

• Develop automation to improve verification efficiency.

Qualifications

• Bachelor's degree in Engineering, Science, or a closely related field
• 4+ years of experience with ASIC design and verification tools, techniques, and methodology

Preferred Qualifications

• Master’s degree in Computer Science, Electrical Engineering, Computer Engineering, or a closely related field
• 6+ years of experience with ASIC design and verification tools, techniques, and methodology
• 6+ years of experience with digital design concepts and RTL languages such as SystemVerilog or Verilog, or VHDL
• 6+ years of experience with computer architecture fundamentals, Object-oriented programming concepts and C or C++ programming skills
• 6+ years of experience with developing block-level testbench environment using SystemVerilog
• 6+ years of experience with verification methodologies through coursework or past experiences such as UVM or OVM and exposure to Assertion based Formal Verification
• 6+ years of experience with scripting/automation skills using either Perl or Python
• Experience with AMBA Bus protocol (AXI/AHB/APB etc) is desirable (not mandatory)
• Knowledge or experience with Assertion Based Formal Verification is desirable (not mandatory)

Minimum Qualifications

• Bachelor\'s degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

OR

• Master\'s degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.

OR

• PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

Additional Information

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, Qualcomm is committed to providing an accessible process. You may e-mail [e-mail] or call Qualcomm\'s toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to updates on applications or resume inquiries).

EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.

Qualcomm expects its employees to abide by all applicable policies and procedures, including security requirements regarding protection of confidential information, to the extent permissible by law.

Pay range and Other Compensation & Benefits: $140,000.00 - $210,000.00

The above pay scale reflects the broad range for this job code and location. Salary is one component of total compensation, which may include a discretionary bonus program and annual RSU grants. Our benefits package is designed to support your success at work, at home, and at play. Your recruiter can discuss details about Qualcomm benefits.

If you would like more information about this role, please contact Qualcomm Careers.