ASIC Design Verification Engineer

AnySilicon; Santa Clara (CA); On-site; USD 140,000 - 210,000; Full time

Job summary

Meta in Santa Clara, CA is seeking an experienced ASIC Design Verification Engineer to join its Infrastructure team, focusing on IP/SoC verification for data center applications. You will develop verification plans, build test benches, and drive closure with metrics across PCIe, DDR, and Ethernet IP to ensure design quality.

You will collaborate with cross-functional teams, implement UVM-based verification environments from scratch, and leverage Python/TCL/Shell scripting to create robust

Qualifications

• Minimum 8 years of IP/sub-system or SoC level verification experience using SystemVerilog UVM/OVM or C/C++ based verification.
• Experience leading verification of complex IPs such as PCIe, RoCE, DDR, HBM, Ethernet, and cache controllers.
• Proficiency in Python, TCL, Perl, and Shell for building verification environments.

Responsibilities

• Define and implement IP/SoC verification plans and build verification test benches.
• Develop functional tests based on the verification test plan.
• Drive Design Verification to closure based on defined metrics, including functional and code coverage.
• Debug and resolve functional failures in collaboration with the Design team.
• Collaborate with cross-functional teams to ensure design quality meets verification goals.
• Implement continuous improvements in Design Verification using the latest methodologies and tools.

Skills

SystemVerilog UVM

C/C++ verification

Functional test planning

Test bench development

Tools

Python scripting

TCL

Perl

Shell scripting

Job description

Meta, 1180 Discovery Way, Sunnyvale, CA 94089

Job Description

Meta is seeking an experienced ASIC Design Verification Engineer to join its Infrastructure organization, focusing on developing IP and System On Chip (SoC) solutions for data center applications. This role involves working within an agile team to ensure the verification closure of design modules and sub-systems, utilizing various methodologies to achieve high-quality designs.

Responsibilities

• Define and implement IP/SoC verification plans and build verification test benches.
• Develop functional tests based on the verification test plan.
• Drive Design Verification to closure based on defined metrics, including functional and code coverage.
• Debug and resolve functional failures in collaboration with the Design team.
• Collaborate with cross-functional teams to ensure design quality meets verification goals.
• Implement continuous improvements in Design Verification using the latest methodologies and tools.

Qualifications

• 8 years of experience in IP/sub-system and/or SoC level verification using SystemVerilog UVM/OVM methodologies and/or C/C++ based verification.
• Experience leading verification of complex IPs like PCIe, RoCE, DDR, HBM, Ethernet, and Cache controllers.
• Proficiency in EDA tools and scripting languages (Python, TCL, Perl, Shell) for building verification environments.

Skills

• Experience with SV Assertions, Formal, and Emulation verification techniques.
• Familiarity with ARM/RISC-V based sub-systems or SoCs.
• Ability to build relationships with cross-functional teams.
• Experience in micro-architectural performance verification.
• Knowledge of revision control systems like Mercurial, Git, or SVN.
• Track record of achieving 'first-pass success' in ASIC development cycles.
• Experience in architecting Design Verification infrastructure and executing full verification cycles.
• Familiarity with Data-center applications including Video, AI/ML, and Networking designs.
• Experience in verifying GPU/CPU designs.Development of UVM based verification environments from scratch.