Senior ASIC Verification Engineer – SoC for Data Centers

Meta; Menlo Park (CA); On-site; USD 178,000 - 250,000; Full time

Benefits offered by this job

Bonus

Equity

Benefits

Job summary

Meta is seeking an experienced ASIC Design Verification Engineer to join the Infrastructure organization in Menlo Park, CA. You will verify IP/SoC blocks, develop UVM-based test benches, and drive closure through coverage metrics, employing Formal and Emulation techniques as needed to reach a bug-free design.

You will work with cross-functional teams across design, model, emulation, and silicon validation to ensure first-pass silicon success for data-center applications.

Qualifications

• 8+ years of experience in IP/sub-system and/or SoC level verification using SystemVerilog UVM/OVM or C/C++ based verification.
• Experience in leading verification of SoC/chiplet or complex IPs (PCIe, RoCE, DDR, HBM, Ethernet, Cache controllers, NoC).
• Proficiency with Python, TCL, Perl or Shell scripts used to build verification flows.

Responsibilities

• Define and implement IP/SoC verification plans and build test benches for verification.
• Develop functional tests based on the verification plan and drive closure with metrics.
• Debug and root-cause functional failures in collaboration with the design team.
• Collaborate with cross-functional teams (Design, Model, Emulation, Silicon validation) to meet verification goals.
• Develop and drive continuous verification improvements using modern methodologies and tools.

Skills

IP/SoC verification

SystemVerilog UVM

C/C++ verification

Python scripting

Verification planning

Tools

Git

Mercurial

EDA tools

Job description

Meta is seeking an experienced ASIC Design Verification Engineer to join the Infrastructure organization in Menlo Park, CA. You will verify IP/SoC blocks, develop UVM-based test benches, and drive closure through coverage metrics, employing Formal and Emulation techniques as needed to reach a bug-free design.

You will work with cross-functional teams across design, model, emulation, and silicon validation to ensure first-pass silicon success for data-center applications.