SoC Verification Engineer for Next-Gen Data Center ASICs

Meta; Sunnyvale (CA); On-site; USD 130,000 - 210,000; Full time

Job summary

Meta in Sunnyvale, CA is seeking an ASIC Design Verification Engineer to help build IP/SoC verification for data center applications. You will work in an agile team with experienced engineers and use UVM-based benches, formal methods, and emulation to achieve bug-free designs.

You will collaborate with Design, Emulation and silicon validation teams, drive verification closure, and contribute to first-pass silicon success by applying best practices in verification and coverage metrics.

Responsibilities

• Define and implement IP/SoC verification plans.
• Build verification test benches to enable IP/sub-system/SoC verification.
• Develop functional tests based on the verification plan.
• Drive design verification to closure with metrics for test plan, functional and code coverage.
• Debug and root-cause functional failures, partnering with the design team.
• Collaborate with cross-functional teams to ensure design quality and verification coverage.
• Drive continuous verification improvements using modern methodologies and tools.

Job description

Meta in Sunnyvale, CA is seeking an ASIC Design Verification Engineer to help build IP/SoC verification for data center applications. You will work in an agile team with experienced engineers and use UVM-based benches, formal methods, and emulation to achieve bug-free designs.

You will collaborate with Design, Emulation and silicon validation teams, drive verification closure, and contribute to first-pass silicon success by applying best practices in verification and coverage metrics.