ASIC Design/Verification Engineer

Salt; San Francisco (CA); Hybrid; USD 140,000 - 200,000; Full time

Job summary

Salt in Sunnyvale, CA seeks an experienced ASIC Design and/or Verification Engineer (Sr. to Principal) for a hybrid role. You will architect and verify modules for high-performance networking chips, write detailed specs, and implement RTL using Verilog/SystemVerilog.

Collaborate with the physical design team for timing closure, create coverage with SVA, and mentor junior engineers to ensure full block validation and robust netlists.

Qualifications

• Experience leading high-performance subsystems from specification to final netlist.
• Proficient in Verilog/SystemVerilog coding.
• Knowledge of computer architecture and networking protocols.
• Strong written and verbal communication skills.
• Proficiency in Perl/Python.

Responsibilities

• Architect/verify complex modules and subsystems used in high performance networking chips.
• Write detailed functional and micro-architecture specifications for your module.
• Implement the design/verification using Verilog or System Verilog.
• Write functional coverage/SVA to help verification catch corner case bugs.
• Collaborate with Physical Design team for timing closure and fix RTL timing as needed.
• Work with Design/Verification teams to ensure full validation of your block.
• Show leadership and provide guidance to new engineers and interns.

Skills

Verilog/SystemVerilog

Leadership

Computer architecture

Networking protocols

Perl/Python

Education

Bachelor’s degree in Engineering

Master’s degree strongly desired

Tools

Synthesis tools

Lint tools

ASIC development tools

Job description

ASIC Design and/or Verification Engineers (Sr. to Principal)

Hybrid - Sunnyvale, CA

Job Family Definition:

Designs, analyzes, develops, modifies and evaluates components and hardware systems. Determines architecture and logic design, design verification through software developed for component and system simulation and builds physical implementations through development of multidimensional designs involving the layout of complex integrated circuits. Analyzes designs to establish operating data, conducts experimental tests and evaluates results to enable prototype and production solutions. May direct support personnel in the preparation of detailed design, design testing and prototype fabrication.

Responsibilities:

• Architect/verify complex modules and subsystems used in high performance networking chips.
• Write detailed functional as well as the micro-architecture specification for your module with that meet the power/area/performance targets.
• Implement the design/verification using Verilog or System Verilog
• Write functional coverage/SVA to help verification catch corner case bugs.
• Make sure your module meets the power targets by using state-of-the-art power reduction techniques during architecture and implementation phases.
• Work with Physical design team for timing closure. Fix timing in RTL to meet the frequency target.
• Collaborate with the Design/Verification team to make sure your block is fully validated.
• Show leadership and provide guidance to new college-grad/junior engineers and interns.

Recommended skills

• Bachelor’s degree in Engineering required (Master’s strongly desired) with 4-15+ years of relevant experience.
• Demonstrated skills in leading and implementing high performance subsystems from specification to final netlist.
• Knowledge of Computer Architecture/networking protocols through prior work is strongly desired.
• Strong coding skills in Verilog/System Verilog through previous work experience are necessary.
• Knowledge of synthesis/lint and other tools used in typical ASIC development process is highly desired.
• Excellent written and verbal communications skills is necessary.
• Knowledge of Perl/Python is strongly desired.