Design Verification Engineer (Junior to Principal)

Judge Group, Inc.; Saint Paul (MN); On-site; USD 130,000 - 220,000; Full time

Job summary

The Judge Group, Inc. is seeking a Senior ASIC Design Verification Engineer to provide technical leadership across advanced digital, mixed-signal, ASIC, SoC, and FPGA verification programs.

This highly visible role requires defining verification strategy, scalable methodologies, mentoring teams, and delivering silicon-ready results. You will lead planning, architecture, and execution of verification across complex designs, establishing methodologies, driving coverage closure, and guiding

Qualifications

• BS or MS in EE/CE or related field required.
• 12+ years in ASIC/SoC/FPGA verification with leadership.
• Deep expertise in SystemVerilog and UVM.

Responsibilities

• Lead end-to-end verification strategy, planning, execution, and signoff for ASIC/SoC/FPGA programs.
• Define verification architecture, methodologies, testbench frameworks, coverage strategies, and signoff criteria.
• Develop reusable verification environments using SystemVerilog, UVM, assertions, constrained-random techniques, and directed testing.
• Create and review verification plans, functional coverage models, scoreboards, monitors, checkers, sequences, and reusable verification IP.
• Drive verification closure through functional coverage, code coverage, assertion coverage, regression results, defect metrics, and quality indicators.
• Investigate and resolve complex issues across RTL, testbenches, firmware, gate-level simulations, emulation, and system-level environments.
• Collaborate with architecture, design, analog/mixed-signal, firmware, FPGA, and program teams to ensure complete verification coverage.
• Serve as the technical verification lead during architecture reviews, design reviews, customer engagements, and signoff activities.
• Provide verification estimates, resource planning, and technical input for new business opportunities, proposals, and program pursuits.
• Mentor and guide verification engineers through technical reviews, methodology development, best practices, and hands-on debugging support.
• Enhance verification efficiency through automation, scripting, reusable infrastructure, and process improvements.
• Evaluate and implement industry-standard verification tools and methodologies across simulation, formal verification, emulation, FPGA prototyping, and verification management solutions.
• Support program execution by identifying technical risks, tracking verification progress, and communicating status to engineering and program leadership.

Skills

SystemVerilog

UVM

Verification strategy

Coverage closure

Constrained-random

Assertions

Regression testing

Python scripting

Debugging RTL

Mentoring

Cross-functional collaboration

Education

Bachelor’s or Master’s degree in Electrical or Computer Engineering

Tools

SystemVerilog

UVM framework

Formal verification

Emulation

Gate-level simulation

Verification IP

Job description

Location: St. Paul, MN Salary: $130,000.00 USD Annually – $220,000.00 USD Annually Description:
We are seeking a Junior – Principal ASIC Design Verification Engineer to provide technical leadership across advanced digital, mixed-signal, ASIC, SoC, and FPGA verification programs. This is a highly visible role for a seasoned verification professional who excels at defining verification strategy, building scalable methodologies, solving complex technical challenges, and mentoring engineering teams.

As an ASIC Design Verification Engineer, you will lead the planning, architecture, and execution of verification efforts for complex ASIC, SoC, subsystem, IP, and FPGA designs. You will establish verification methodologies, drive coverage closure, ensure design quality and functionality, and support successful silicon delivery.

Working cross-functionally with architecture, RTL design, analog/mixed-signal, firmware, FPGA, emulation, and program management teams, you will serve as both a hands‑on technical contributor and a verification leader. You will help define best practices, guide critical verification activities, and influence technical decision‑making across programs.

Key Responsibilities

• Lead end-to-end verification strategy, planning, execution, and signoff for ASIC, SoC, subsystem, IP, and FPGA development programs.
• Define verification architecture, methodologies, testbench frameworks, coverage strategies, and signoff criteria.
• Develop and maintain reusable verification environments using SystemVerilog, UVM, assertions, constrained-random techniques, and directed testing methodologies.
• Create and review verification plans, functional coverage models, scoreboards, monitors, checkers, sequences, and reusable verification IP.
• Drive verification closure through analysis of functional coverage, code coverage, assertion coverage, regression results, defect metrics, and quality indicators.
• Investigate and resolve complex issues across RTL, testbenches, firmware, gate-level simulations, emulation platforms, and system-level environments.
• Collaborate closely with architecture, design, analog/mixed-signal, firmware, FPGA, and program teams to ensure complete and efficient verification coverage.
• Serve as the technical verification lead during architecture reviews, design reviews, customer engagements, and signoff activities.
• Provide verification estimates, resource planning, and technical input for new business opportunities, proposals, and program pursuits.
• Mentor and guide verification engineers through technical reviews, methodology development, best practices, and hands‑on debugging support.
• Enhance verification efficiency through automation, scripting, reusable infrastructure, and continuous process improvements.
• Evaluate and implement industry-standard verification tools and methodologies, including simulation, formal verification, emulation, FPGA prototyping, and verification management solutions.
• Support program execution by identifying technical risks, tracking verification progress, and communicating status to engineering and program leadership.

Required Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical discipline.
• 12 years of ASIC, SoC, or FPGA verification experience with demonstrated leadership of complex verification projects.
• Deep expertise in SystemVerilog and UVM-based verification methodologies.
• Strong experience developing block-level, subsystem-level, and SoC-level verification environments.
• Proven ability to create verification plans, coverage models, constrained-random test environments, directed tests, assertions, and regression strategies.
• Strong understanding of verification closure processes, including functional coverage, code coverage, assertion coverage, defect analysis, and signoff methodologies.
• Extensive experience debugging complex RTL and verification environment issues.
• Proficiency with scripting and automation tools, including Python, Perl, Tcl, Shell, or Make.
• Experience with industry-standard EDA tools for simulation, debug, coverage analysis, and verification management.
• Demonstrated technical leadership and mentoring experience within verification organizations.
• Excellent communication, collaboration, and stakeholder management skills.
• Ability to work effectively across multidisciplinary engineering teams and customer-facing environments.

Preferred Qualifications

• Experience with high-speed protocols and interfaces, including PCIe, CXL, DDR, LPDDR, Ethernet, USB, MIPI, AMBA, AXI, CHI, and UCIe.
• Experience supporting proposal development, technical solutioning, program scoping, or pre-sales activities within a design services organization.
• Knowledge of formal verification, assertion-based verification, and property checking methodologies.
• Experience with gate-level simulation, low-power verification, UPF/CPF flows, reset verification, and X-propagation analysis.
• Familiarity with emulation platforms, FPGA prototyping, hardware/software co-verification, and post-silicon validation.
• Understanding of mixed-signal verification techniques and methodologies.
• Experience working directly with customers, external stakeholders, or engineering services organizations.