ASIC Design Verification Engineer

Meta; Sunnyvale (CA); On-site; USD 130,000 - 210,000; Full time

Job summary

Meta in Sunnyvale, CA is seeking an ASIC Design Verification Engineer to help build IP/SoC verification for data center applications. You will work in an agile team with experienced engineers and use UVM-based benches, formal methods, and emulation to achieve bug-free designs.

You will collaborate with Design, Emulation and silicon validation teams, drive verification closure, and contribute to first-pass silicon success by applying best practices in verification and coverage metrics.

Responsibilities

• Define and implement IP/SoC verification plans.
• Build verification test benches to enable IP/sub-system/SoC verification.
• Develop functional tests based on the verification plan.
• Drive design verification to closure with metrics for test plan, functional and code coverage.
• Debug and root-cause functional failures, partnering with the design team.
• Collaborate with cross-functional teams to ensure design quality and verification coverage.
• Drive continuous verification improvements using modern methodologies and tools.

Job description

ASIC Design Verification Engineer# ASIC Design Verification EngineerSunnyvale, CA+1 locationHardware+ 1 moreApply nowMeta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for data center applications.As a Design Verification Engineer, you will be part of an agile team working with experienced engineers across the industry, focused on developing ASIC solutions for Meta’s data center applications. You will be responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure. Along with traditional simulation, you will use other approaches like Formal and Emulation to achieve a bug-free design. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success.---## ASIC Design Verification Engineer Responsibilities* Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification* Develop functional tests based on verification test plan* Drive Design Verification to closure based on defined verification metrics on the test plan, functional, and code coverage* Debug, root-cause and resolve functional failures in the design, partnering with the Design team* Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring design quality meets defined verification and coverage goals* Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry