ASIC Verification Engineer

Insight Global; San Jose (CA); On-site; USD 140,000 - 210,000; Full time

Job summary

Insight Global seeks a Design Verification Engineer to join Cisco's silicon one group in San Jose, CA. You will develop UVM-based verification environments and create comprehensive verification plans across block and system levels.

You’ll design assertions, traffic generators, agents and scoreboards, collaborate with cross-functional teams to assess testability, and lead debugging efforts for complex challenges.

Qualifications

• UVM-based verification experience and testbench development.
• Experience in ASIC or SOC verification and test plan development.
• Familiarity with verification methodologies from block to system level.

Responsibilities

• Develop and implement UVM verification environments.
• Create verification plans at block and system levels.
• Design assertions, traffic generators, agents and scoreboards.
• Collaborate on testability needs and verification requirements.
• Lead debug efforts and propose solutions for complex issues.

Skills

UVM testbench development

Test plans development

ASIC/SoC verification

Debugging complex tech

End-to-end verification methodology

AI-based CAD efficiency ideas

Education

Bachelor's degree in Electrical Engineering or related field

Tools

Python

Perl

SystemVerilog

C programming

Formal verification techniques

UCIe/PCIe knowledge

Job description

Job Description

Join our innovative team developing next-generation silicon solutions for Cisco's silicon one group.

We are seeking a collaborative Design Verification Engineer with 5-12 years of industry experience to help create cutting edge System-on-Chip (SoC) designs delivered first time right. You will work in a collaborative environment, participating in architectural decisions and verification strategies that directly impact product success. This team values diverse perspectives and creative problem-solving approaches to deliver exceptional customer experiences.

What You'll Do:

• Develop and implement Universal Verification Methodology (UVM) based verification environments.
• Create comprehensive verification plans at both block and system levels.
• Design and implement verification components including assertions, traffic generators, agents, and scoreboards.
• Collaborate with cross-functional teams to evaluate design testability and verification requirements.
• Lead debug efforts and provide solutions for complex technical challenges.

Skills and Requirements

• Bachelor's degree in Electrical Engineering or a related field.
• UVM Based testbench development.
• Experience in ASIC or SOC verification.
• Demonstrated experience in developing test plans and verification infrastructure.
• Practical knowledge of verification methodologies from block level to system level.
• C coding for firmware delivery for post silicon bringupExperience with formal verification techniques including abstraction and end-to-end checking.
• Experience with industry-standard tools and scripting languages (Python or Perl) for automation.
• System Verilog coding and debug.
• AI based CAD efficiency improvisation initiativesHigh speed serial protocols preferred UCIe, PCIE etcAnalog debug experience including DAC/ADC & calibrations white-box verification.

We are a company committed to creating diverse and inclusive environments where people can bring their full, authentic selves to work every day. We are an equal employment opportunity/affirmative action employer that believes everyone matters. Qualified candidates will receive consideration for employment without regard to race, color, ethnicity, religion, sex (including pregnancy), sexual orientation, gender identity and expression, marital status, national origin, ancestry, genetic factors, age, disability, protected veteran status, military or uniformed service member status, or any other status or characteristic protected by applicable laws, regulations, and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request to [e-mail].