ASIC Design Engineer, Pixel IP for AI/ML Acceleration

Apple Inc.; Sunnyvale (CA); Hybrid; USD 150,000 - 278,000; Full time

Benefits offered by this job

Stock programs

RSU awards

Stock Purchase Plan

Medical and dental coverage

Retirement benefits

Product discounts

Education expense reimbursement

Discretionary bonuses

Job summary

Apple Inc. in Sunnyvale seeks an experienced ANE design/integration engineer to advance RTL designs for high-speed subsystems within the Pixel IP ANE team.

You will collaborate with architecture, verification, power, and physical design groups to ensure robust performance and testability across Apple Neural Engine projects. The role requires deep knowledge of computer architecture, bus topologies (AMBA), and strong experience in synthesis, timing, and DFT/BIST interfaces.

Qualifications

• BS + 3 years of experience
• Extensive knowledge of AMBA bus topology
• Experience with large, high-speed compute systems
• Good knowledge base on Clock Domain Crossing designs
• Experience with Synthesis
• Experience with Static Timing Analysis
• Experience working with Power Intent

Responsibilities

• Do RTL design on high-speed, high-performance subsystem.
• Collaborate with design verification and formal verification teams to fully verify design and performance.
• Work with physical design and static timing teams to produce high-quality netlists through synthesis.
• Analyze clock domain crossing designs for correctness.
• Collaborate with DFT and BIST teams to ensure the design can be fully tested.

Skills

RTL design

Clock domain crossing

AMBA bus protocols

Synthesis

Static timing analysis

DFT/BIST

Power integrity

Education

BS degree in Electrical Engineering or equivalent

Tools

Synthesis tools

Formal verification tools

Power analysis tools

Job description

Apple Inc. in Sunnyvale seeks an experienced ANE design/integration engineer to advance RTL designs for high-speed subsystems within the Pixel IP ANE team.

You will collaborate with architecture, verification, power, and physical design groups to ensure robust performance and testability across Apple Neural Engine projects. The role requires deep knowledge of computer architecture, bus topologies (AMBA), and strong experience in synthesis, timing, and DFT/BIST interfaces.