Senior ASIC Front-End Engineer, Pixel IP

MaziCTools; United States; Remote; USD 176.000 - 312.000; Vollzeit

Benefits dieser Stelle

Medical and dental coverage

Retirement benefits

Discounted Apple products

Tuition reimbursement

Relocation assistance

Zusammenfassung

Apple in Cupertino, California, is seeking an ASIC Design Engineer for the Pixel IP design team to craft high-performance, low-power pixel processing engines. You will collaborate with cross-functional teams to integrate large IP/SoC subsystems and ensure timely delivery of cutting-edge visuals.

The role emphasizes front-end RTL design using Verilog/SystemVerilog, clock-domain considerations, DFT, and close partnership with Physical Design and Verification teams to achieve timing closure and

Qualifikationen

• BS and 10+ years in ASIC/SoC front-end RTL design.
• Experience with SystemVerilog and Verilog for large IP/SoC.
• Familiarity with AMBA protocols and floorplanning/timing closure.
• Strong collaboration and communication skills.

Aufgaben

• Integrate large pixel-processing subsystems using SystemVerilog in a high-performance on-chip network.
• Write detailed micro-architectural specifications for pixel engines.
• Perform front-end implementation including synthesis, clock domain checks, STA, and power analysis.
• Collaborate with Physical Design for floorplanning and timing closure.
• Work with design verification and formal verification teams to debug and verify functionality.

Kenntnisse

Verilog / SystemVerilog

RTL design

Synthesis & STA

Low-power design

AMBA protocols

DFT integration

Python / TCL / Perl

Clock domain design

Cross-functional collaboration

Verification collaboration

Ausbildung

Bachelor's degree in Electrical Engineering or related

Tools

Synthesis tools

STA tools

DFT tools

Jobbeschreibung

Apple in Cupertino, California, is seeking an ASIC Design Engineer for the Pixel IP design team to craft high-performance, low-power pixel processing engines. You will collaborate with cross-functional teams to integrate large IP/SoC subsystems and ensure timely delivery of cutting-edge visuals.

The role emphasizes front-end RTL design using Verilog/SystemVerilog, clock-domain considerations, DFT, and close partnership with Physical Design and Verification teams to achieve timing closure and