Senior ASIC Front-End Designer — SoC & Pixel IP (Stock Options)

Apple Inc.; Sunnyvale (CA); Sur place; USD 129 000 - 195 000; Plein temps

Avantages offerts par ce poste

Apple Benefits

Relocation assistance

Employee Stock Purchase Plan

Tuition reimbursement

Discounted products

Résumé du poste

Apple Inc. is seeking an ASIC Design Engineer for the Pixel IP design team in Sunnyvale to create high-performance, power-efficient SoCs. You will develop RTL and engage with architecture, design and verification to deliver cutting-edge pixel processing for images and video.

The role emphasizes front-end design, synthesis, timing and area optimizations, cross-functional collaboration, and thorough verification. Competitive compensation and comprehensive benefits.

Qualifications

• Extensive experience in ASIC front-end RTL design using Verilog and SystemVerilog.
• Familiarity with AMBA protocols (AXI/AHB/APB).
• Experience in low-power design techniques and cross-functional collaboration.

Responsabilités

• Design digital hardware by writing RTL or using high-level synthesis with embedded assertions.
• Write detailed micro-architectural specifications.
• Collaborate with architecture, design and verification teams to maximize performance and minimize power/area.
• Synthesize design and optimize for power, timing and area.
• Work with design verification and formal verification teams to debug and verify functionality.
• Manage deliverables and coordinate with cross-functional teams.

Connaissances

Verilog

SystemVerilog

AMBA Protocols

Front-end ASIC design

Python/Perl/TCL scripting

Power optimization

Formation

Bachelors Degree in EE/CE

Outils

Verilog

SystemVerilog

Description du poste

Apple Inc. is seeking an ASIC Design Engineer for the Pixel IP design team in Sunnyvale to create high-performance, power-efficient SoCs. You will develop RTL and engage with architecture, design and verification to deliver cutting-edge pixel processing for images and video.

The role emphasizes front-end design, synthesis, timing and area optimizations, cross-functional collaboration, and thorough verification. Competitive compensation and comprehensive benefits.