ASIC Design Engineer - Pixel IP ANE

Apple; Sunnyvale (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Apple in Sunnyvale is seeking a seasoned hardware design engineer to contribute to next-generation Pixel IP ANE. You will design RTL for high-speed subsystems and collaborate with cross-functional teams across architecture, verification, power, and physical design.

The role emphasizes timing, testability, and robust integration for devices used by millions. Applicants should have a BS in EE/CE with 10+ years of hands-on experience in ASIC/SoC design, strong AMBA knowledge, and proficiency in

Qualifications

• BS degree and 10+ years of relevant hardware/ASIC design experience.

Responsibilities

• Design RTL for high-speed, high-performance subsystems.
• Collaborate with verification, power, physical design teams.
• Analyze clock domain crossing for correctness.
• Work with DFT and BIST teams to ensure testability.
• Support synthesis and static timing analysis to deliver quality netlists.

Skills

AMBA bus topologies

Clock Domain Crossing

Synthesis

Static Timing Analysis

Power Intent

DFT/BIST

Education

Bachelor's degree in Electrical Engineering or Computer Engineering

Tools

AMBA

DFT

BIST

Power Integrity

Job description

Summary

Are you interested in working on complex, high performance machine learning system? As part of our Hardware Technologies group, you’ll help to design our next-generation Apple Neural Engine. You will work on designs that will contribute to the future generation of products on AI/ML aspect, that will be used by millions! As AI and ML are making a huge difference in our life, joining our team and contribute to this trailblazing field with high growth.In this is a highly visible role, you’ll be able to collaborate with many cross-functional teams, making impactful differences to Apple products.

Description

As part of the Pixel IP ANE design and integration engineer in pixel IP team, you will work closely with different cross functional team, including architecture, verification, power, physical design and more. Extensive knowledge of computer architecture is required, including bus topologies and protocols, such as AMBA. This role includes the following tasks:

• Doing RTL design on high speed, high performance subsystem.
• Working with design verification and formal verification teams to fully verify design and performance
• Working with physical design and static timing team to produce high quality netlist through synthesis.
• Analyze clock domain crossing design for correctness
• Working with DFT, and BIST team to ensure design can be fully tested.

Minimum Qualifications

BS + 10 years of experience

Preferred Qualifications

Extensive knowledge of bus topology, such as AMBAExperience working on large, high speed, compute systemGood knowledge base on Clock Domain Crossing designsExperience with SynthesisExperience with Static Timing AnalysisExperience working with Power Intent