Senior ASIC Designer: IP Integration & Pixel Processing

Apple Inc.; Sunnyvale (CA); Hybrid; USD 185,000 - 325,000; Full time

Job summary

Apple Inc. is seeking an ASIC Design Engineer to join the Pixel IP design team.

You will develop high-performance, low-power pixel processing engines and integrate complex subsystems across architecture, design, and verification groups. You will author micro-architectural specs, craft RTL with assertions, collaborate with physical design for timing closure, and support verification to ensure correct functionality and performance.

Qualifications

• Bachelor's degree and 10+ years of relevant industry experience.
• Experience with ASIC/FPGA design methodology and floorplanning with timing closure.
• Experience with multiple clock and reset domains.
• Familiarity with AMBA protocols (AXI, AHB, APB).
• Experience in low-power design and UPF power intent.
• Proficiency in scripting (Python, Perl, TCL).
• Datapath/pixel-centric design experience a plus.
• Strong collaboration and communication skills.

Responsibilities

• Write detailed micro-architectural and integration specifications.
• Perform digital hardware design by writing RTL with embedded assertions and cover points.
• Collaborate with physical design to optimize timing, area and power in silicon.
• Follow industry best practices for power, clock and reset domains.
• Work with verification and formal verification teams to debug and verify functionality.
• Manage deliverables and support cross-functional engineering efforts.

Skills

IP/SoC design

Clock & reset domains

Scripting (Python, Perl, TCL)

Collaboration

Education

Bachelor's degree

Tools

AMBA (AXI/AHB/APB)

UPF power intent

Python/Perl/TCL scripting

Job description

Apple Inc. is seeking an ASIC Design Engineer to join the Pixel IP design team.

You will develop high-performance, low-power pixel processing engines and integrate complex subsystems across architecture, design, and verification groups. You will author micro-architectural specs, craft RTL with assertions, collaborate with physical design for timing closure, and support verification to ensure correct functionality and performance.