Senior ASIC Design Engineer - Pixel IP for Neural Engine

Apple; Sunnyvale (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Apple in Sunnyvale is seeking a seasoned hardware design engineer to contribute to next-generation Pixel IP ANE. You will design RTL for high-speed subsystems and collaborate with cross-functional teams across architecture, verification, power, and physical design.

The role emphasizes timing, testability, and robust integration for devices used by millions. Applicants should have a BS in EE/CE with 10+ years of hands-on experience in ASIC/SoC design, strong AMBA knowledge, and proficiency in

Qualifications

• BS degree and 10+ years of relevant hardware/ASIC design experience.

Responsibilities

• Design RTL for high-speed, high-performance subsystems.
• Collaborate with verification, power, physical design teams.
• Analyze clock domain crossing for correctness.
• Work with DFT and BIST teams to ensure testability.
• Support synthesis and static timing analysis to deliver quality netlists.

Skills

AMBA bus topologies

Clock Domain Crossing

Synthesis

Static Timing Analysis

Power Intent

DFT/BIST

Education

Bachelor's degree in Electrical Engineering or Computer Engineering

Tools

AMBA

DFT

BIST

Power Integrity

Job description

Apple in Sunnyvale is seeking a seasoned hardware design engineer to contribute to next-generation Pixel IP ANE. You will design RTL for high-speed subsystems and collaborate with cross-functional teams across architecture, verification, power, and physical design.

The role emphasizes timing, testability, and robust integration for devices used by millions. Applicants should have a BS in EE/CE with 10+ years of hands-on experience in ASIC/SoC design, strong AMBA knowledge, and proficiency in