ASIC Design Engineer

BayOne Solutions; Sunnyvale (CA); On-site; USD 140,000 - 170,000; Full time

Job summary

BayOne Solutions in Sunnyvale seeks an experienced RTL design engineer to translate functional specs into micro-architecture and implement high‑performance RTL using Verilog and SystemVerilog. You will develop functional coverage and SVA assertions, collaborate with the Verification team to identify corner-case bugs, and partner with the Physical Design team on timing closure.

The role includes mentoring new graduates and interns to cultivate design excellence.

Responsibilities

• Translate functional specs into micro-architecture and implement RTL designs using Verilog/SystemVerilog.
• Develop functional coverage and SVA assertions to identify corner-case bugs with the Verification team.
• Collaborate with Physical Design on floorplanning and timing closure to meet frequency targets.
• Provide technical leadership and mentoring to new graduates and interns.

Tools

Verilog

SystemVerilog

SVA

Job description

• Micro-architecture & RTL Design: Translate functional specifications into detailed micro-architecture and implement high-performance designs using Verilog/SystemVerilog while meeting power and area targets.
• Design Verification: Develop functional coverage and SVA assertions to identify corner-case bugs and collaborate closely with the Verification team to ensure robust block validation.
• Timing & Physical Design: Partner with the Physical Design team on floorplanning and timing closure, proactively identifying and resolving RTL timing issues to meet frequency targets.
• Technical Leadership & Mentoring: Drive design excellence while mentoring and guiding new college graduates and interns, with opportunities to develop technical and leadership skills