RTL Design Engineer

Insight Global; North Reading (MA); On-site; USD 120,000 - 180,000; Full time

Job summary

Insight Global is seeking an RTL Design Engineer to join a cutting-edge Silicon Technology Engineering team. You will own ASIC/SoC design blocks from concept through silicon validation and collaborate with architects, verification, physical design, software, and silicon bring-up teams.

The role emphasizes developing microarchitecture and RTL in Verilog/SystemVerilog, supporting timing closure and post-silicon optimization in a fast-paced environment.

Qualifications

• 5+ years of ASIC/SoC RTL design experience.
• Experience taking designs through implementation and silicon validation.
• Solid understanding of digital design fundamentals and ASIC development flows.
• Proven ability to work cross-functionally in a fast-paced environment.

Responsibilities

• Own ASIC/SoC design blocks from specification to silicon bring-up.
• Develop microarchitecture and RTL using Verilog/SystemVerilog.
• Collaborate with architecture, verification, physical design, and software teams.
• Support verification, implementation, timing closure, and silicon validation activities.
• Design and debug complex digital logic including FSMs, FIFOs, datapaths, and control logic.
• Contribute to post-silicon debug and design optimization.

Skills

RTL design

Verilog/SystemVerilog

ASIC/SoC design

Silicon validation

Cross-functional collaboration

Timing closure

Job description

Insight Global is seeking an RTL Design Engineer to join a cutting-edge Silicon Technology Engineering team developing advanced-node mixed-signal ASICs for next-generation SoC and Memory Test products.

In this role, you will own ASIC design blocks from concept through silicon validation, partnering closely with architects, verification engineers, physical design teams, software engineers, and silicon bring-up teams throughout the full chip development lifecycle.

Key Responsibilities:

• Own ASIC/SoC design blocks from specification to silicon bring-up
• Develop microarchitecture and RTL using Verilog/SystemVerilog
• Collaborate with architecture, verification, physical design, and software teams
• Support verification, implementation, timing closure, and silicon validation activities
• Design and debug complex digital logic including FSMs, FIFOs, datapaths, and control logic
• Contribute to post-silicon debug and design optimization

Required Qualifications:

• 5+ years of ASIC/SoC RTL design experience
• Experience taking designs through implementation and silicon validation
• Solid understanding of digital design fundamentals and ASIC development flows
• Proven ability to work cross-functionally in a fast-paced environment