Senior Digital Designer

Lumicity; San Francisco (CA); On-site; USD 150,000 - 190,000; Full time

Job summary

Lumicity in San Francisco seeks an experienced Digital Design Engineer to design, verify, and optimize next-generation semiconductor IP. You will lead RTL implementation, model development, and architecture collaboration with cross-functional teams to ensure robust chip integration.

Ideal candidates bring 4+ years in digital design, strong SystemVerilog/Python skills, and hands-on experience with RTL and verification strategies.

Qualifications

• MS or PhD in Electrical Engineering, Computer Engineering, or a related field.
• 4+ years of industry experience in digital design, RTL, microarchitecture, or architecture development.
• Strong hands-on experience with RTL design and digital simulation.
• Experience with memory, control, or other complex digital subsystems is a plus.
• Understanding of computer architecture fundamentals and hardware/software interfaces.
• Experience with modeling and simulation using languages such as Python, Verilog-A, SystemVerilog, or related tools.
• Proficiency in Verilog/SystemVerilog and solid RTL coding practices.
• Familiarity with digital implementation concepts, timing constraints, and EDA development flows.
• Experience with simulation, synthesis, linting, static timing analysis, and related EDA tools.

Responsibilities

• Design, develop, and verify digital IP for next-generation semiconductor products.
• Contribute to architecture and development of complex digital control systems.
• Own portions of the design process, including architecture, RTL implementation, interfaces, and integration.
• Develop and integrate behavioral and functional models to support design and verification.
• Collaborate with circuit and system engineers to ensure seamless integration between hardware blocks.
• Develop and execute verification strategies for digital designs and system models.
• Participate in design reviews and contribute to improving RTL design practices, methodologies, and processes.
• Work closely with cross-functional engineering teams to define architectures, interfaces, and system requirements.
• Support chip-level simulation, integration, debugging, and validation activities.

Skills

RTL design

Digital design

Microarchitecture

Python

SystemVerilog

Verilog

Hardware/Software interfaces

Debugging complex hardware

Simulation & verification

EDA tool flows

Education

MS or PhD in Electrical Engineering, Computer Engineering, or related field

Tools

Python

Verilog/SystemVerilog

SystemVerilog

Job description

What You'll Bring

• Design, develop, and verify digital IP for next-generation semiconductor products.
• Contribute to the architecture and development of complex digital control systems.
• Own portions of the design process, including architecture, RTL implementation, interfaces, and integration.
• Develop and integrate behavioral and functional models to support design and verification.
• Collaborate with circuit and system engineers to ensure seamless integration between hardware blocks.
• Develop and execute verification strategies for digital designs and system models.
• Participate in design reviews and contribute to improving RTL design practices, methodologies, and processes.
• Work closely with cross-functional engineering teams to define architectures, interfaces, and system requirements.
• Support chip-level simulation, integration, debugging, and validation activities.

• MS or Ph.D. in Electrical Engineering, Computer Engineering, or a related field, with 4+ years of industry experience in digital design, RTL, microarchitecture, or architecture development.
• Strong hands-on experience with RTL design and digital simulation.
• Experience working with memory, control, or other complex digital subsystems is a plus.
• Understanding of computer architecture fundamentals and hardware/software interfaces.
• Experience with modeling and simulation using languages such as Python, Verilog-A, SystemVerilog, or related tools.
• Proficiency in Verilog/SystemVerilog and solid RTL coding practices.
• Familiarity with digital implementation concepts, timing constraints, and EDA development flows.
• Experience with simulation, synthesis, linting, static timing analysis, and related EDA tools.
• Ability to debug complex hardware designs and work across multiple levels of abstraction.