Design Engineer - ASIC/RTL

Infobahn Softworld Inc; San Jose (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

Infobahn Softworld Inc in San Jose, CA is seeking an experienced RTL Design Engineer to help design leading edge SoCs in advanced CMOS processes. You'll contribute across architecture, micro-architecture, verification, and timing closure to deliver silicon.

The ideal candidate has hands-on ASIC flow experience, RTL coding, and familiarity with ARM cores and IO interfaces, plus strong communication, documentation, and technical leadership to guide cross-functional teams.

Qualifications

• SoC design experience in ASIC flow including RTL coding, debugging/verification, and supporting synthesis and timing closure.
• Experience with ARM cores and IO interfaces.
• Strong communication, documentation, time management, and leadership abilities.

Responsibilities

• Lead and participate in the design of leading edge SoCs in advanced digital CMOS processes.
• Contribute to chip definition, architecture development, and micro-architectural specs.
• Convert micro-architectural specs to logic implementation, verification, emulation, debug, synthesis, and timing closure.
• Interface with physical execution, software, and silicon bring-up teams.

Skills

SoC Architecture

ASIC design

RTL coding

timing closure

ARM cores

I/O interfaces

Communication skills

Documentation skills

Time management

Technical leadership

Job description

• The work will expose the designer to a number of IP including ARM cores, Ethernet, DDR, DMA, PCIE, SATA and the clients internal IPs.
• Successful candidates will be responsible for leading, and participating in, the design of leading edge SoCs in advanced digital CMOS processes.
• Our RTL Design Engineers are expected contribute to all aspects of SoC design including Chip definition, Architecture development and modeling, Development of micro-architectural specifications, Conversion of micro-architectural specifications to logic implementation, Verification, emulation, debug, synthesis, and timing closure, Interfacing with physical execution, software, and silicon bring-up teams.

Experience:

• SoC Architecture; knowledge and hand-on experience from industry ASIC design flow including RTL coding, debugging/verification, and supporting synthesis and timing closure.
• Working knowledge of ARM cores and other I/O standard interfaces.
• An ideal candidate would also exhibit: Strong communication and documentation skills, Good organizational, time management and multitasking skills, Strong initiative and discipline to follow-through, technical leadership.