VLSI Design Engineer

Retym, Inc; Austin (TX); On-site; USD 100,000 - 130,000; Full time

Job summary

Retym, Inc is seeking a talented VLSI Design Engineer/Micro-architect in Austin, Texas. This role involves designing cutting-edge communication systems, collaborating on cross-functional teams, and participating in all design stages including RTL coding and verification.

The ideal candidate will have over 5 years of experience, strong skills in Verilog/System-Verilog, and a solid educational background in electrical or computer engineering. A self-motivated team player with good interpersonal skills is essential for success in this role.

Qualifications

• +5 years of experience as ASIC/VLSI digital design engineer.
• Strong Verilog/System-Verilog experience.
• Familiar with simulation tools/environments, verification methodologies.

Responsibilities

• Work closely with Algorithm and Architecture teams.
• Understand and translate high-level algorithmic requirements into hardware.
• Participate in all design stages: Micro-architecture definition, RTL coding, synthesis.

Skills

Verilog/System-Verilog

ASIC/VLSI Design

Simulation Tools

Interpersonal Skills

Self-motivated

Education

BS/MS in EE/CE from lead universities

Tools

Python

Perl

TCL

Job description

Overview

We are looking for talented and experienced VLSI Design Engineers/Micro-architects. As a VLSI Digital Design Engineer/Micro-architect, you\'ll have the opportunity to design highly sophisticated, innovative new cutting edge communication systems from scratch.

Responsibilities

• Work closely with Algorithm and Architecture teams
• Understand and translate high-level algorithmic requirements into efficient hardware implementations.
• Learn and analyze relevant protocols and standards
• Interpret protocol specifications (e.g., Ethernet, etc.) and apply them accurately in design.
• Participate in all design stages: Micro-architecture definition; RTL coding (using Verilog/SystemVerilog); synthesis-friendly coding and timing-aware design
• Collaborate cross-functionally: Verification team for testbench development, debug support, and functional coverage closure; DFT team to ensure design is scan-insertable, supports ATPG, BIST, etc.; Backend/Physical design team for floorplanning, timing closure, and routing feedback
• Participate in Design Reviews: Present and defend design decisions in peer and formal reviews.
• Perform Synthesis and Timing Analysis: Generate synthesis constraints (SDC), run synthesis, and analyze timing reports.
• Debug and Fix Functional/Timing Issues: Collaborate in post-silicon or pre-silicon debug; use waveforms, assertions, and logic analyzers.
• Optimize for Area, Power, and Performance (PPA): Identify bottlenecks and opportunities for improvement within RTL.
• Documentation: Maintain clear design documentation for reusability and reference (e.g., micro-architecture specs, interface docs).
• Contribute to IP/SoC Integration: Work on integrating design blocks into larger systems and handling system-level interfaces.
• Participate in Silicon Bring-up and Validation (optional but valuable): Support bring-up of first silicon and assist with post-silicon validation, if applicable.
• Keep up-to-date with Industry Trends and Tools: Learn new EDA tools, languages, and methodologies (e.g., CDC, Linting, Formal Verification).

Qualifications / Requirements

• +5 years of experience as ASIC/VLSI digital design engineer
• Strong Verilog/System-Verilog experience
• Familiar with simulation tools/environments, verification methodologies
• Strong team player, solid interpersonal skills
• Entrepreneurial can-do attitude, self-motivated, able to work independently
• BS/MS in EE/CE from lead universities

Preferred Background

• Familiar with advanced design practices (Clock/Voltage domain crossing, Low Power Design, DFT)
• Design DSP-oriented blocks
• Ethernet (100G and above)
• Scripting experience using Python, Perl, TCL