System-on-Chip Design Engineer

Belcan; Bellevue (WA); On-site; USD 180,000 - 260,000; Full time

Job summary

Qualifications

• Experience with RTL design, verification, and related methodologies.
• Proven skills in SystemVerilog design, verification, and assertions.
• Hands-on use of industry-standard EDA tools for RTL, linting, and code quality.

Responsibilities

• Review and validate RTL design, verification, and physical implementation tasks.
• Support development of chip design training environments across design, verification, and physical implementation domains.
• Define benchmarks for engineering tasks and assess solutions.
• Collaborate with building teams, model training teams, and domain experts.
• Drive continuous improvement of task realism and engineering standards.
• Explain design decisions and tradeoffs involving power, performance, and area.

Skills

RTL Design

SystemVerilog Design & Verification

SystemVerilog Assertions (SVA)

Education

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or equivalent

Tools

Synopsys VCS

Design Compiler

Job description

Are you passionate about digital silicon design and verification? We're looking for an experienced Chip Design Engineer to help shape and validate realistic semiconductor design training environments while working across the full chip design lifecycle.

Education: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or equivalent

Key Responsibilities

• Review and validate RTL design, verification, and physical implementation tasks for technical accuracy and realism.
• Support development of chip design training environments across design, verification, and physical implementation domains.
• Assess solutions and define technical skill benchmarks for engineering tasks.
• Collaborate closely with building teams, model training teams, and domain experts.
• Drive continuous improvement of task quality, realism, and engineering standards.
• Explain design decisions, methodologies, and tradeoffs involving power, performance, area, and verification.

Required Qualifications

• 10+ years of Digital ASIC or SoC design experience.
• Strong expertise in:
  • RTL Design
  • SystemVerilog Design & Verification
  • SystemVerilog Assertions (SVA)
• Hands-on experience with Synopsys EDA tools:
  • VCS
  • Design Compiler
• Deep understanding of front-end design, verification, and physical design flows.
• Ability to communicate complex technical concepts and engineering tradeoffs effectively.
• Strong project management, stakeholder engagement, and collaboration skills.

Preferred Qualifications

• Full RTL-to-GDSII flow experience.
• Static Timing Analysis (STA).
• Design for Testability (DFT).
• Experience with industry-standard EDA tool suites.

What We're Looking For

We're seeking a detail-oriented engineer who can combine strong technical expertise with excellent communication and collaboration skills. The ideal candidate will be comfortable working independently, partnering with cross-functional teams, and driving excellence in chip design training and evaluation programs.