Senior RTL Design Engineer

Highbrow Technology Inc; Mountain View (CA); On-site; USD 150,000 - 210,000; Full time

Job summary

Highbrow Technology Inc. in Mountain View seeks a Senior RTL Design Engineer to design digital IP blocks, develop micro-architectures, and drive designs from RTL to GDSII, collaborating with Verification and Physical Design teams across the ASIC flow.

You will work on high-speed interfaces such as DDR, PCIe, UCIe, and Ethernet, using Python for automation, and contribute to architecture and design reviews while supporting integration and customer engagements throughout development.

Qualifications

• 8+ years of industry experience in digital IC/SoC design.
• Experience leading or contributing to complex SoC development projects.
• Strong RTL design expertise using VHDL, Verilog, or SystemVerilog.
• Solid understanding of digital design fundamentals and synchronous design principles.
• Experience working with cross-functional engineering teams throughout the ASIC design flow.
• Experience in high-speed interfaces such as DDR, PCIe, UCIe, and Ethernet.
• Design automation and scripting using Python.

Responsibilities

• Design and develop digital logic for internal platform and customer SoC projects.
• Create functional specifications and develop micro-architectures for digital IP blocks.
• Develop high-quality RTL using Verilog, VHDL, and/or SystemVerilog.
• Perform block-level design, simulation, debugging, and optimization.
• Collaborate with Design Verification and Physical Design teams to take designs from RTL to GDSII.
• Support integration, bring-up, and customer engagements throughout the development lifecycle.
• Drive technical excellence and contribute to architecture and design reviews.

Skills

RTL design

Digital IC/SoC design

Cross-functional collaboration

Synchronous design principles

Python scripting

Tools

Verilog

VHDL

SystemVerilog

DDR

PCIe

UCIe

Ethernet

Python

Job description

We are looking for an experienced Senior RTL Design Engineer to join the team and help deliver innovative silicon solutions for internal platforms and customer programs..

Key Responsibilities:

• Design and develop digital logic for internal platform and customer SoC projects.
• Create functional specifications and develop micro-architectures for digital IP blocks.
• Develop high-quality RTL using Verilog, VHDL, and/or SystemVerilog.
• Perform block-level design, simulation, debugging, and optimization.
• Collaborate with Design Verification and Physical Design teams to take designs from RTL to GDSII.
• Support integration, bring-up, and customer engagements throughout the development lifecycle.
• Drive technical excellence and contribute to architecture and design reviews..

Required Qualifications:

• 8+ years of industry experience in digital IC/SoC design.
• Proven experience leading or contributing to complex SoC development projects.
• Strong RTL design expertise using VHDL, Verilog, or SystemVerilog.
• Solid understanding of digital design fundamentals and synchronous design principles.
• Experience working with cross-functional engineering teams throughout the ASIC design flow.
• Experience in high-speed interfaces such as DDR, PCIe, UCIe, and Ethernet
• Design automation and scripting using Python