RTL Design Engineer: Microarchitecture to Tapeout

Normal Computing Corporation; Palo Alto (CA); On-site; USD 180,000 - 260,000; Full time

Job summary

Normal Computing is seeking an RTL Design Engineer to write and own synthesizable SystemVerilog RTL across datapath to memory interfaces. You will work with architecture to translate specifications into practical microarchitectures and collaborate with verification and physical design for timing and area goals.

You will join a team that values strong debugging and close collaboration, with experience taping out silicon. Open collaboration across ASIC/SoC domains is encouraged.

Qualifications

• Hands-on experience writing production RTL in SystemVerilog and closing it through synthesis and place-and-route.
• Experience closing coverage to a high level and supporting tapeout activities.
• Background with datapaths, pipelines, or custom logic where microarchitecture was not fully specified upfront.

Responsibilities

• Write and own synthesizable RTL across datapath logic, control, and memory interfaces.
• Translate specifications into implementable microarchitectures with architecture teams.
• Collaborate with verification and physical design to meet timing and area constraints.
• Participate in design reviews and support tapeout preparation and bring-up.

Skills

SystemVerilog RTL

Microarchitecture

ASIC/SoC design

Formal verification

Debugging

Cross-team collaboration

Tapeout experience

Tools

DFT tooling

Place-and-route

Job description

Normal Computing is seeking an RTL Design Engineer to write and own synthesizable SystemVerilog RTL across datapath to memory interfaces. You will work with architecture to translate specifications into practical microarchitectures and collaborate with verification and physical design for timing and area goals.

You will join a team that values strong debugging and close collaboration, with experience taping out silicon. Open collaboration across ASIC/SoC domains is encouraged.