Physical Design Engineer

ACL Digital; San Jose (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

ACL Digital is seeking an experienced RTL/physical design engineer in San Jose, CA. The role focuses on timing-driven design flows, SDC constraint development, and QoR optimization across synthesis and signoff.

You will perform static timing analysis, signoff checks, and drive closure through floorplanning with Cadence Innovus, including advanced nodes (5nm or below). The ideal candidate will have hands-on experience with Cadence Genus, Fusion, Tempus, and Innovus in fast-paced environments and

Qualifications

• Strong experience in RTL synthesis using Cadence Genus/Fusion compiler, including SDC constraint development and QoR optimization (timing, area, power).
• Hands-on expertise in Static Timing Analysis using Tempus, including setup/hold closure, MMMC scenarios, OCV, and timing signoff concepts.
• Ability to analyze and debug timing violations across synthesis and floorplan stages and drive closure.
• Experience in block-level floorplanning using Cadence Innovus, or fusion compiler including macro placement, IO planning, utilization.

Responsibilities

• Analyze timing and power closure across RTL synthesis and floorplan phases.
• Collaborate with design teams to debug timing violations and drive signoff readiness.

Skills

RTL synthesis

QoR optimization

SDC constraints

Static Timing Analysis

Timing signoff

Floorplanning

Cadence Innovus

5nm nodes

Tools

Cadence Genus

Cadence Fusion Compiler

Cadence Innovus

Tempus

Job description

• Strong experience in RTL synthesis using Cadence Genus/Fusion compiler, including SDC constraint development and QoR optimization (timing, area, power)
• Hands-on expertise in Static Timing Analysis using Tempus, including setup/hold closure, MMMC scenarios, OCV, and timing signoff concepts
• Ability to analyze and debug timing violations across synthesis and floorplan stages and drive closure
• Experience in block-level floorplanning using Cadence Innovus, or fusion compiler including macro placement, IO planning, utilization,
• Experience in advanced nodes (5nm or below) with ability to work in a fast-paced, execution-driven environment