ASIC Design Engineer - RTL, Verification, Timing & Mentoring

BayOne Solutions; Sunnyvale (CA); On-site; USD 140,000 - 170,000; Full time

Job summary

BayOne Solutions in Sunnyvale seeks an experienced RTL design engineer to translate functional specs into micro-architecture and implement high‑performance RTL using Verilog and SystemVerilog. You will develop functional coverage and SVA assertions, collaborate with the Verification team to identify corner-case bugs, and partner with the Physical Design team on timing closure.

The role includes mentoring new graduates and interns to cultivate design excellence.

Responsibilities

• Translate functional specs into micro-architecture and implement RTL designs using Verilog/SystemVerilog.
• Develop functional coverage and SVA assertions to identify corner-case bugs with the Verification team.
• Collaborate with Physical Design on floorplanning and timing closure to meet frequency targets.
• Provide technical leadership and mentoring to new graduates and interns.

Tools

Verilog

SystemVerilog

SVA

Job description

BayOne Solutions in Sunnyvale seeks an experienced RTL design engineer to translate functional specs into micro-architecture and implement high‑performance RTL using Verilog and SystemVerilog. You will develop functional coverage and SVA assertions, collaborate with the Verification team to identify corner-case bugs, and partner with the Physical Design team on timing closure.

The role includes mentoring new graduates and interns to cultivate design excellence.