AI-Enhanced RTL Chip Design Engineer

TenX Semi; San Francisco (CA); Hybrid; USD 140,000 - 210,000; Full time

Job summary

TenX Semi seeks a Chip Design Engineer to drive RTL development for strategic customer engagements. You will optimize designs for power, performance, and area, collaborating with AI systems to ensure production-ready RTL.

Role combines hands-on RTL design with exposure to cutting-edge AI technology and reference implementations used to train models. Responsibilities include implementing PCIe, DDR, AXI blocks for customers.

Qualifications

• 5+ years of experience designing production RTL.
• Solid understanding of pipeline design, FSMs, arbitration, and data flow.

Responsibilities

• Design RTL for strategic customer engagements, writing clean, synthesizable Verilog/SystemVerilog.
• Optimize designs for power, performance and area to support royalty-generating designs.
• Support synthesis and timing closure; ensure RTL timing-friendly implementation.
• Improve AI-generated designs by reviewing and enhancing RTL for production quality.
• Develop high-quality reference implementations used for training AI models.
• Implement protocol blocks (PCIe, DDR, AXI, etc.) for customer requirements.

Skills

RTL Design Experience

Micro-Architecture Understanding

Synthesis Awareness

Debug Skills

PPA Intuition

Collaborative Mindset

Education

MS in Electrical Engineering or Computer Science

Tools

Verdi

SimVision

Design Compiler

Genus

Job description

TenX Semi seeks a Chip Design Engineer to drive RTL development for strategic customer engagements. You will optimize designs for power, performance, and area, collaborating with AI systems to ensure production-ready RTL.

Role combines hands-on RTL design with exposure to cutting-edge AI technology and reference implementations used to train models. Responsibilities include implementing PCIe, DDR, AXI blocks for customers.