Chip Design Engineer

TenX Semi; San Francisco (CA); Hybrid; USD 140,000 - 210,000; Full time

Job summary

TenX Semi seeks a Chip Design Engineer to drive RTL development for strategic customer engagements. You will optimize designs for power, performance, and area, collaborating with AI systems to ensure production-ready RTL.

Role combines hands-on RTL design with exposure to cutting-edge AI technology and reference implementations used to train models. Responsibilities include implementing PCIe, DDR, AXI blocks for customers.

Qualifications

• 5+ years of experience designing production RTL.
• Solid understanding of pipeline design, FSMs, arbitration, and data flow.

Responsibilities

• Design RTL for strategic customer engagements, writing clean, synthesizable Verilog/SystemVerilog.
• Optimize designs for power, performance and area to support royalty-generating designs.
• Support synthesis and timing closure; ensure RTL timing-friendly implementation.
• Improve AI-generated designs by reviewing and enhancing RTL for production quality.
• Develop high-quality reference implementations used for training AI models.
• Implement protocol blocks (PCIe, DDR, AXI, etc.) for customer requirements.

Skills

RTL Design Experience

Micro-Architecture Understanding

Synthesis Awareness

Debug Skills

PPA Intuition

Collaborative Mindset

Education

MS in Electrical Engineering or Computer Science

Tools

Verdi

SimVision

Design Compiler

Genus

Job description

San Francisco Bay Area, CA · Hybrid · Full-time

We are looking for a Chip Design Engineer who works on strategic customer engagements, developing custom IP and optimizing designs for power, performance, and area. You will collaborate closely with our AI systems, providing the domain expertise that ensures AI-generated designs meet real-world requirements.

In this role, you will combine hands-on RTL design with exposure to cutting-edge AI technology. You will help shape how AI and human expertise work together in chip design. Your designs will go into production at the world's leading technology companies.

What You Will Do

• Design RTL for Customer Projects: Implement RTL for strategic customer engagements. You will write clean, synthesizable, timing-aware Verilog/SystemVerilog.
• Optimize for PPA: Analyze and optimize designs for power, performance, and area. Your optimizations will contribute to royalty-generating designs.
• Support Synthesis and Timing: Work through synthesis and timing closure. You understand what makes RTL synthesizable and how to fix timing violations.
• Improve AI-Generated Designs: Review and enhance AI-generated RTL for production quality. Your feedback will improve model accuracy.
• Develop Reference Implementations: Create high-quality reference designs that become training data for our AI models.
• Implement Protocol Blocks: Build protocol implementations (PCIe, DDR, AXI, etc.) for customer requirements.

What You Bring (Required)

• RTL Design Experience: You have 5+ years of experience designing production RTL. You write clean, readable, synthesizable Verilog/SystemVerilog.
• Micro-Architecture Understanding: You have solid understanding of pipeline design, FSMs, arbitration, and data flow. You can translate architecture specs into RTL.
• Synthesis Awareness: You have experience with synthesis tools (Design Compiler, Genus). You understand what makes RTL timing-friendly.
• Debug Skills: You can read waveforms, trace signal paths, and debug complex logic issues. You have experience with Verdi, SimVision, or similar tools.
• PPA Intuition: You understand power-performance-area tradeoffs. You can make informed design decisions based on PPA goals.
• Collaborative Mindset: You work well with verification engineers, architects, and AI engineers. You communicate clearly and give/receive feedback well.

Bonus Points (Preferred)

• Experience at leading semiconductor companies (Intel, AMD, NVIDIA, Qualcomm, Broadcom, Marvell, MediaTek).
• Protocol implementation experience (PCIe, DDR, AXI, AHB, APB, CHI).
• Physical design awareness (floor planning, clock tree, routing congestion).
• Background in accelerator, SoC, or high-performance computing design.
• Familiarity with AI/ML concepts and interest in AI-assisted design.
• MS in Electrical Engineering or Computer Science.

Why Join Us

You will be at the forefront of AI-assisted chip design—a fundamental transformation in how chips are built. Your designs will go into production at top tech companies. You'll learn cutting-edge AI while applying your chip design expertise, building skills that will define the future of the industry.